-
公开(公告)号：US12198769B2
公开(公告)日：2025-01-14
申请号：US17741074
申请日：2022-05-10
Applicant: SanDisk Technologies LLC
Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.
-
2.发明公开公开(公告)号：US20230368850A1
公开(公告)日：2023-11-16
申请号：US17741074
申请日：2022-05-10
Applicant: SanDisk Technologies LLC
CPC classification number: G11C16/3445 , G11C16/3495 , G11C16/16 , G11C16/26 , G11C16/08
Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.
-
公开(公告)号：US20220246208A1
公开(公告)日：2022-08-04
申请号：US17166612
申请日：2021-02-03
Applicant: SanDisk Technologies LLC
IPC: G11C11/56 , G11C16/04 , G11C16/26 , H01L25/065 , H01L23/00
Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.
-
公开(公告)号：US10229744B2
公开(公告)日：2019-03-12
申请号：US15816546
申请日：2017-11-17
Applicant: SanDisk Technologies LLC
Inventor： Deepanshu Dutta , Idan Alrod , Huai-Yuan Tseng , Amul Desai , Jun Wan , Ken Cheah , Sarath Puthenthermadam
IPC: G11C16/04 , G11C16/34 , G11C16/26 , G11C16/16 , G11C8/08 , G11C16/08 , G11C29/02 , G11C11/56 , G11C29/12
Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
-
公开(公告)号：US10026486B1
公开(公告)日：2018-07-17
申请号：US15451186
申请日：2017-03-06
Applicant: SanDisk Technologies LLC
Inventor： Deepanshu Dutta , Idan Alrod , Huai-Yuan Tseng , Amul Desai , Jun Wan , Ken Cheah , Sarath Puthenthermadam
Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of the memory cells can shift depending on the coupled up state of the word lines. In one approach, for a read operation, a representative word line voltage in a block is detected and a corresponding set of read voltages is selected. In another approach, a pre-read voltage pulse is applied to a selected word line in response to a read command, just prior to reading the selected cells. In another approach, a voltage pulse is periodically applied to each word line in a block to provide the word lines in a coupled up state. In another approach, a soft erase is performed after a read operation to prevent coupling up of the word lines.
-
Patent Agency Ranking
公开(公告)号：US12125537B2
公开(公告)日：2024-10-22
申请号：US17502398
申请日：2021-10-15
Applicant: SanDisk Technologies LLC
CPC classification number: G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0483
Abstract: The memory device includes a control circuitry that is communicatively coupled to memory cells are arranged in a plurality of word lines. The control circuitry is configured to perform a first programming pass on a selected word line. The first programming pass includes a plurality of programming loops, each of which includes the application of a programming pulse (Vpgm). The programming pulse voltage is increased between programming loops of the first programming pass by a step size. The step size is a first step size between two programming loops of the first programming pass and is a second step size that is different than the first step size between two other programming loops of the first programming pass. The control circuitry is also configured to perform a second programming pass to further program the memory cells of the selected word line to the plurality of data states.
-
公开(公告)号：US11972812B2
公开(公告)日：2024-04-30
申请号：US17549431
申请日：2021-12-13
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Jiahui Yuan , Jun Wan , Deepanshu Dutta
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
Abstract: A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
-
公开(公告)号：US20230187000A1
公开(公告)日：2023-06-15
申请号：US17549431
申请日：2021-12-13
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Jiahui Yuan , Jun Wan , Deepanshu Dutta
CPC classification number: G11C16/3459 , G11C16/3404 , G11C16/102 , G11C16/26 , G11C16/08
Abstract: A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
-
公开(公告)号：US11626160B2
公开(公告)日：2023-04-11
申请号：US17166612
申请日：2021-02-03
Applicant: SanDisk Technologies LLC
Abstract: Technology for sensing non-volatile memory cells in which one or more sense nodes are charged to a sense voltage having a magnitude that improves sensing accuracy. One sense node may be charged to different sense voltages when sensing different memory cells at different times. Multiple sense nodes may be charged to a corresponding multiple different sense voltages when sensing different memory cells at the same time. The one or more sense nodes are allowed to discharge based on respective currents of memory cells for a pre-determined time while applying a reference voltage to the memory cells. The Vts of the selected memory cells are assessed based on respective voltages on the one or more of sense nodes after the pre-determined time. Different sensing voltages may be used based on bit line voltage, bit line resistance, distance of memory cells from the sense node, or other factors.
-
公开(公告)号：US10115737B2
公开(公告)日：2018-10-30
申请号：US15893157
申请日：2018-02-09
Applicant: SanDisk Technologies LLC
Inventor： Hoon Cho , Jun Wan , Ching-Huang Lu
IPC: H01L27/11582 , H01L29/792 , H01L29/788 , H01L29/423 , H01L29/40 , H01L27/11556 , H01L21/28
Abstract: Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.023 seconds)
