公开(公告)号：US20120013357A1

公开(公告)日：2012-01-19

申请号：US13233894

申请日：2011-09-15

Applicant: Sang Kwon LEE ,  Bong Seok Han

Inventor： Sang Kwon LEE ,  Bong Seok Han

IPC: G01R31/10

CPC classification number: G11C29/06 ,  G11C29/022 ,  G11C29/14 ,  G11C29/46 ,  G11C29/56 ,  G11C29/56012

Abstract: A semiconductor device comprises a burn-in test circuit configured to receive a flag signal for a burn-in test, generate a toggled output enable signal, and drive a first input/output line to toggle a signal on the first input/output line, and a switching device connected between a bit line and a second input/output line for transferring a signal on the bit line to the second input/output line in response to the output enable signal.

Abstract translation: 半导体器件包括老化测试电路，其被配置为接收用于老化测试的标志信号，产生切换的输出使能信号，以及驱动第一输入/输出线来切换第一输入/输出线上的信号， 以及连接在位线和第二输入/输出线之间的开关装置，用于响应于输出使能信号将位线上的信号传送到第二输入/输出线。

公开(公告)号：US20110050290A1

公开(公告)日：2011-03-03

申请号：US12844175

申请日：2010-07-27

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: H03K3/00

CPC classification number: H03K19/018585 ,  H03K19/01721

Abstract: An output driver circuit includes a pre-driver unit and a first driving unit. The pre-driver unit is configured to generate a driving selection signal and a driving signal from a pre-driving signal in response to a group selection signal and a code signal. The first driving unit is configured to drive a data pad in response to the driving selection signal and the driving signal.

Abstract translation: 输出驱动器电路包括预驱动器单元和第一驱动单元。 预驱动器单元被配置为响应于组选择信号和代码信号从预驱动信号产生驱动选择信号和驱动信号。 第一驱动单元被配置为响应于驱动选择信号和驱动信号来驱动数据焊盘。

公开(公告)号：US20120014190A1

公开(公告)日：2012-01-19

申请号：US13241885

申请日：2011-09-23

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: G11C11/402 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/222 ,  G11C7/225 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2211/4065

Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

Abstract translation: 半导体存储器件的刷新信号产生电路包括一个标志信号发生器，该标志信号发生器响应于刷新信号和一个预充电信号产生一个标志信号;一个时钟使能信号缓冲器，其基于外部时钟使能产生第一和第二缓冲器使能信号 响应于标志信号的信号，以及片选信号缓冲器，其响应于标志信号，基于外部片选信号产生内部片选信号。

公开(公告)号：US20110026344A1

公开(公告)日：2011-02-03

申请号：US12649475

申请日：2009-12-30

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: G11C7/00 ,  G11C8/08

CPC classification number: G11C7/1048

Abstract: The data control circuit includes an input/output line and a driver. The input/output line precharging circuit precharges a global input/output line to a predetermined voltage when either a reading operation or a writing operation is inoperative. The driver includes a number of MOS transistors and drives the global input/output line in response to receiving data from a local input/output line and a complementary local input/output line during the reading operation.

Abstract translation: 数据控制电路包括输入/​​输出线和驱动器。 当读取操作或写入操作不起作用时，输入/输出线预充电电路将全局输入/输出线预充电到预定电压。 驱动器包括多个MOS晶体管，并响应于在读取操作期间从本地输入/输出线路和互补的本地输入/输出线路接收数据来驱动全局输入/输出线路。

公开(公告)号：US20120113728A1

公开(公告)日：2012-05-10

申请号：US13096669

申请日：2011-04-28

Applicant: Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

Inventor： Kyoung Hwan KWON ,  Tae Jin KANG ,  Sang Kwon LEE

IPC: G11C7/10 ,  G11C8/18

CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222

Abstract: A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal.

Abstract translation: 数据输入电路包括时钟采样单元，最终时钟产生单元和写入锁存信号产生单元。 采样单元被配置为产生包括在写入等待时间之后产生的脉冲的移位信号，并且在从产生移位信号的脉冲的时间开始的脉冲串周期期间，通过对内部时钟进行采样来产生采样时钟。 最终时钟生成单元被配置为通过与采样时钟同步地锁存移位信号来产生电平信号，并且响应于突发信号从电平信号产生最终时钟。 写锁存信号生成单元被配置为通过锁存最终时钟来产生使能信号，并且响应于使能信号产生用于锁存和输出对准数据的写锁存信号。

公开(公告)号：US20120218832A1

公开(公告)日：2012-08-30

申请号：US13359997

申请日：2012-01-27

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1096 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1087 ,  G11C11/4096

Abstract: A data transmission circuit includes: a driving voltage generation unit configured to generate a driving voltage having a lower level than an external driving voltage; a switch unit configured to transmit the driving voltage when any one of a write enable signal and a read enable signal is enabled; and a data transmission unit configured to be driven by receiving the driving voltage, transmit a signal of a DQ pad as data in response to the write enable signal, and transmit the data to the DQ pad in response to the read enable signal.

Abstract translation: 数据传输电路包括：驱动电压产生单元，被配置为产生具有比外部驱动电压低的电平的驱动电压; 开关单元，被配置为当使能写入信号和读使能信号中的任何一个被使能时发送驱动电压; 以及数据传输单元，被配置为通过接收驱动电压来驱动，响应于写使能信号，将DQ焊盘的信号作为数据发送，并且响应于读使能信号将数据发送到DQ焊盘。

公开(公告)号：US20110102025A1

公开(公告)日：2011-05-05

申请号：US12825799

申请日：2010-06-29

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: H03K3/00

CPC classification number: H03K19/00361 ,  H03K19/018585

Abstract: The data output circuit includes a first decoder, a second decoder, a first selective output circuit, a second selective output circuit, and an output driver. The first decoder is configured to generate a pull-up selection signal by decoding a pull-up code. The second decoder is configured to generate a pull-down selection signal by decoding a pull-down code. The first selective output circuit is configured to select and output a voltage level of a pull-up level signal in response to the pull-up selection signal. The second selective output circuit is configured to select and output a voltage level of a pull-down level signal in response to the pull-down selection signal. The output driver is configured to drive output data in response to receiving a pre-pull-up signal and a pre-pull-down signal.

Abstract translation: 数据输出电路包括第一解码器，第二解码器，第一选择输出电路，第二选择输出电路和输出驱动器。 第一解码器被配置为通过解码上拉代码来生成上拉选择信号。 第二解码器被配置为通过解码下拉码产生下拉选择信号。 第一选择输出电路被配置为响应于上拉选择信号来选择和输出上拉电平信号的电压电平。 第二选择输出电路被配置为响应于下拉选择信号选择并输出下拉电平信号的电压电平。 输出驱动器被配置为响应于接收到预上拉信号和预下拉信号来驱动输出数据。

公开(公告)号：US20130147542A1

公开(公告)日：2013-06-13

申请号：US13570400

申请日：2012-08-09

Applicant: Sang Kwon LEE

Inventor： Sang Kwon LEE

IPC: H01H37/76

CPC classification number: G11C17/16 ,  G06F11/1048

Abstract: A fuse circuit includes a programming fuse signal generation block configured to generate parity signals, logic levels of which are determined according to addresses selected among a plurality of addresses with a programming enable signal enabled, and generate programming fuse signals which are programmed in response to the programming enable signal, the plurality of addresses and the parity signals; a corrected pulse generation block configured to correct an error included in the programming fuse signals and generate corrected pulses; and a fuse unit configured to generate fuse signals which are reprogrammed according to the corrected pulses.

Abstract translation: 熔丝电路包括编程熔丝信号产生块，其被配置为产生奇偶校验信号，其逻辑电平根据在多个地址中选择的地址而被确定，其中编程使能信号使能，并产生编程熔丝信号，其响应于 编程使能信号，多个地址和奇偶校验信号; 校正脉冲发生块，被配置为校正编程熔丝信号中包括的误差并产生校正脉冲; 以及熔丝单元，被配置为产生根据校正的脉冲重新编程的熔丝信号。