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    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS
    1.
    发明申请
    LEAKAGE REDUCTION STRUCTURES FOR NANOWIRE TRANSISTORS 有权
    纳米晶体管的漏电减少结构

    公开(公告)号：US20140264253A1

    公开(公告)日：2014-09-18

    申请号：US13996845

    申请日：2013-03-14

    申请人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    发明人： Seiyon Kim ,  Kelin Kuhn ,  Rafael Rios ,  Mark Armstrong

    IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/786 ,  H01L21/266 ,  H01L29/10 ,  H01L21/265

    CPC分类号： H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

    摘要： A nanowire device of the present description may include a highly doped underlayer formed between at least one nanowire transistor and the microelectronic substrate on which the nanowire transistors are formed, wherein the highly doped underlayer may reduce or substantially eliminate leakage and high gate capacitance which can occur at a bottom portion of a gate structure of the nanowire transistors. As the formation of the highly doped underlayer may result in gate inducted drain leakage at an interface between source structures and drain structures of the nanowire transistors, a thin layer of undoped or low doped material may be formed between the highly doped underlayer and the nanowire transistors.

    摘要翻译： 本描述的纳米线器件可以包括形成在至少一个纳米线晶体管和其上形成纳米线晶体管的微电子衬底之间的高度掺杂的底层，其中高度掺杂的底层可以减少或基本上消除可能发生的泄漏和高栅极电容 在纳米线晶体管的栅极结构的底部。 由于高掺杂底层的形成可能导致在纳米线晶体管的源极结构和漏极结构之间的界面处的栅极感应漏极泄漏，可以在高掺杂底层和纳米线晶体管之间形成未掺杂或低掺杂材料的薄层 。

    INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES
    6.
    发明申请
    INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES 有权
    用于制造纳米器件的内部间隔件的集成方法

    公开(公告)号：US20140001441A1

    公开(公告)日：2014-01-02

    申请号：US13539195

    申请日：2012-06-29

    申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

    发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

    IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00

    CPC分类号： H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

    摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

    摘要翻译： 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。