中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.02 seconds)

    SEMICONDUCTOR DEVICE AND MEMORY DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY DEVICE 有权
    半导体器件和存储器件

    公开(公告)号：US20160225772A1

    公开(公告)日：2016-08-04

    申请号：US15007259

    申请日：2016-01-27

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Masashi TSUBUKU ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Daigo SHIMADA ,  Tsutomu MURAKAWA

    IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

    CPC classification number: H01L29/7869 ,  G11C11/401 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78696

    Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN  ( t ) = V 0 ×  - ( t τ ) β ( 1 )

    Abstract translation: 可以测量微小电流的半导体器件。 半导体器件包括第一晶体管，第二晶体管，节点和电容器。 第一晶体管包括沟道形成区中的氧化物半导体。 该节点电连接到第二晶体管的栅极和电容器的第一端子。 通过在提供电位V0之后关闭第一晶体管，使节点进入电浮动状态。 随着时间的推移，节点的潜在VFN的变化由公式（1）表示。 在公式（1）中，t是节点进入电浮动状态之后的经过时间，τ是以时间为单位的常数，β是大于或等于0.4且小于等于0.6的常数。 V FN（t）= V 0× - （tτ）β（1）

    PROPERTY PREDICTION SYSTEM FOR SEMICONDUCTOR ELEMENT
    4.
    发明申请
    PROPERTY PREDICTION SYSTEM FOR SEMICONDUCTOR ELEMENT 有权

    公开(公告)号：US20220414499A1

    公开(公告)日：2022-12-29

    申请号：US17773868

    申请日：2020-11-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunsuke HOSOUMI ,  Kunihiko SUZUKI ,  Kanta ABE ,  Yuji IWAKI ,  Daigo SHIMADA ,  Etsuko KAMATA

    IPC: G06N5/04 ,  H01L21/66

    Abstract: A property prediction system for a semiconductor element is provided. The property prediction system includes a memory unit, an input unit, a processing unit, and an arithmetic unit. The processing unit has a function of creating a learning data set from first data stored in the memory unit, a function of creating prediction data from second data supplied from the input unit, a function of converting qualitative data (a material name or a compositional formula) into quantitative data (the properties of an element and a composition), and a function of performing extraction or removal on the first data and the second data. The first data includes step lists of first to m-th semiconductor elements (m is an integer of 2 or more) and the properties of the first to m-th semiconductor elements. The second data includes a step list of an (m+1)-th semiconductor element. The arithmetic unit having a function of performing learning and inference of supervised learning performs learning on the basis of the learning data set and makes an inference of a semiconductor element from the prediction data.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140327007A1

    公开(公告)日：2014-11-06

    申请号：US14334012

    申请日：2014-07-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

    IPC: H01L27/12 ,  H01L27/088

    CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

    Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面提供并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160300933A1

    公开(公告)日：2016-10-13

    申请号：US15190677

    申请日：2016-06-23

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shinya SASAGAWA ,  Hitoshi NAKAYAMA ,  Masashi TSUBUKU ,  Daigo SHIMADA

    IPC: H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L27/12 ,  H01L29/45

    CPC classification number: H01L29/66969 ,  H01L22/14 ,  H01L27/088 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/7869

    Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

    Abstract translation: 当制造具有底栅底接触结构的晶体管时，例如，构成源极和漏极的导电层具有三层结构，并且执行两步蚀刻。 在第一蚀刻工艺中，采用其中至少第二膜和第三膜的蚀刻速率高的蚀刻方法，并且进行第一蚀刻处理直到至少第一膜暴露。 在第二蚀刻工艺中，第一膜的蚀刻速率高于第一蚀刻工艺中的蚀刻速率和“下面设置并与第一膜接触的”层的蚀刻速率的蚀刻方法低于 采用第一蚀刻工艺。 当在第二蚀刻工艺之后去除抗蚀剂掩模时，第二膜的侧壁被稍微蚀刻。

Patent Agency Ranking