公开(公告)号：US20250160004A1

公开(公告)日：2025-05-15

申请号：US19024240

申请日：2025-01-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC: H10D99/00 ,  H01L21/02 ,  H10D30/67 ,  H10D86/01 ,  H10D86/40 ,  H10D86/60 ,  H10F39/00

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20240274696A1

公开(公告)日：2024-08-15

申请号：US18606052

申请日：2024-03-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Masashi TSUBUKU

IPC: H01L29/66 ,  H01L21/02 ,  H01L27/12 ,  H01L27/146 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/14616 ,  H01L27/14689 ,  H01L29/7869 ,  H01L29/78696

Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

公开(公告)号：US20240250183A1

公开(公告)日：2024-07-25

申请号：US18626592

申请日：2024-04-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G02F1/1333 ,  G02F1/1337 ,  G02F1/1339 ,  G02F1/1343 ,  H01L21/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66 ,  H10K59/121

CPC classification number: H01L29/7869 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78696 ,  G02F2202/10 ,  H01L21/02565 ,  H10K59/1213

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.

公开(公告)号：US20240243204A1

公开(公告)日：2024-07-18

申请号：US18522543

申请日：2023-11-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L27/12 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66 ,  G11C7/00 ,  G11C19/28 ,  H02M3/07

CPC classification number: H01L29/78609 ,  G06K19/07758 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/0883 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/26 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  G11C7/00 ,  G11C19/28 ,  H01L2223/6677 ,  H02M3/07

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor, With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US20230411410A1

公开(公告)日：2023-12-21

申请号：US18239928

申请日：2023-08-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Masashi TSUBUKU ,  Kosei NODA

IPC: H01L27/12 ,  G09G3/20 ,  G09G3/3291 ,  H01L29/786 ,  H03K19/003 ,  H03K19/096 ,  G11C19/28 ,  H03K17/16 ,  G09G3/36 ,  G11C19/18

CPC classification number: H01L27/1255 ,  G09G3/3233 ,  G09G3/3291 ,  H01L27/1225 ,  H01L29/7869 ,  H01L27/1222 ,  H03K19/00315 ,  H03K19/096 ,  G09G3/2092 ,  G11C19/28 ,  H03K17/161 ,  G09G3/36 ,  G11C19/184 ,  H01L27/124 ,  G09G3/20

Abstract: To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

公开(公告)号：US20230260785A1

公开(公告)日：2023-08-17

申请号：US18137572

申请日：2023-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masashi TSUBUKU ,  Masashi OOTA ,  Yoichi KUROSAWA ,  Noritaka ISHIHARA

IPC: H01L21/02 ,  C23C14/08 ,  C01G15/00 ,  B82Y30/00 ,  C23C14/34 ,  C30B23/08 ,  C30B29/22 ,  H01J37/34 ,  C30B1/04 ,  C30B28/02 ,  C30B29/68 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02631 ,  C23C14/08 ,  C01G15/006 ,  B82Y30/00 ,  C23C14/086 ,  C23C14/3414 ,  C30B23/08 ,  C30B29/22 ,  H01J37/3429 ,  C30B1/04 ,  C30B28/02 ,  C30B29/68 ,  H01L21/02565 ,  H01L21/02609 ,  H01L29/045 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  C01P2002/32 ,  C01P2002/72 ,  C01P2002/85 ,  C01P2004/04 ,  C01P2004/61 ,  C01P2004/62 ,  C01P2004/64 ,  H01J2237/081 ,  H01J2237/3322 ,  H01J2237/3323

Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.

公开(公告)号：US20210366944A1

公开(公告)日：2021-11-25

申请号：US17396832

申请日：2021-08-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Toshinari SASAKI ,  Junichiro SAKATA ,  Masashi TSUBUKU

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/786 ,  H01L29/24 ,  H01L29/423

Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.

公开(公告)号：US20210225887A1

公开(公告)日：2021-07-22

申请号：US17144550

申请日：2021-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masahiro TAKAHASHI ,  Takuya HIROHASHI ,  Masashi TSUBUKU ,  Noritaka ISHIHARA ,  Masashi OOTA

IPC: H01L27/12 ,  H01L29/04 ,  H01L21/66 ,  H01L29/24 ,  G02F1/1368 ,  G01N23/207 ,  H01L29/66 ,  C23C14/08 ,  H01L29/786

Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nmφ and less than or equal to 10 nmφ.

公开(公告)号：US20210143281A1

公开(公告)日：2021-05-13

申请号：US17010151

申请日：2020-09-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Hiroyuki MIYAKE ,  Kei TAKAHASHI ,  Kouhei TOYOTAKA ,  Masashi TSUBUKU ,  Kosei NODA ,  Hideaki KUWABARA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/26 ,  G06K19/077 ,  H01L21/8236 ,  H01L23/66 ,  H01L27/088 ,  H01L29/24 ,  H01L29/66

Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.

公开(公告)号：US20190237585A1

公开(公告)日：2019-08-01

申请号：US16381479

申请日：2019-04-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya HONDA ,  Masashi TSUBUKU ,  Yusuke NONAKA ,  Takashi SHIMAZU ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  G02F1/1337 ,  H01L29/24 ,  H01L29/51 ,  G02F1/1333 ,  H01L27/12 ,  H01L29/66 ,  H01L29/04 ,  G02F1/1339 ,  G02F1/1343

CPC classification number: H01L29/7869 ,  G02F1/133345 ,  G02F1/1337 ,  G02F1/13394 ,  G02F1/134309 ,  G02F2202/10 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/045 ,  H01L29/24 ,  H01L29/51 ,  H01L29/66969 ,  H01L29/78696

Abstract: A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an oxide semiconductor film provided to be in contact with the gate insulating film and overlap with at least the gate electrode, and a source electrode and a drain electrode electrically connected to the oxide semiconductor film. In the oxide semiconductor film, a first region which is provided to be in contact with the gate insulating film and have a thickness less than or equal to 5 nm has a silicon concentration lower than or equal to 1.0 at. %, and a region in the oxide semiconductor film other than the first region has lower silicon concentration than the first region. At least the first region includes a crystal portion.