公开(公告)号：US20240256033A1

公开(公告)日：2024-08-01

申请号：US18569785

申请日：2022-06-20

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiromichi GODO ,  Yoshiyuki KUROKAWA ,  Seiko INOUE ,  Kazuaki OHSHIMA ,  Shunpei YAMAZAKI

IPC: G06F3/01 ,  G06T1/20 ,  G06T7/73 ,  G06V10/141 ,  G06V40/18 ,  H04N23/611 ,  H04N23/617 ,  H04N23/90

CPC classification number: G06F3/013 ,  G06T1/20 ,  G06T7/75 ,  G06V10/141 ,  G06V40/193 ,  H04N23/611 ,  H04N23/617 ,  H04N23/90 ,  G06T2207/10048 ,  G06T2207/20081 ,  G06T2207/30041 ,  G06T2207/30201

Abstract: An electronic device that enables smooth communication is provided. The electronic device includes a display portion including a first camera; a second camera; and an image processing portion. The second camera is positioned in a region not overlapping with the display portion. The first camera has a function of generating a first image of a subject, and the second camera has a function of generating a second image of the subject. The image processing portion includes a generator that performs learning using training data. The training data includes an image including a person's face. The image processing portion has a function of making the first image clear when the first image is input to the generator and a function of tracking the gaze of the subject on the basis of the second image.

公开(公告)号：US20220246615A1

公开(公告)日：2022-08-04

申请号：US17612873

申请日：2020-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki OHSHIMA ,  Hitoshi KUNITAKE ,  Takahiro FUKUTOME

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.

公开(公告)号：US20170133064A1

公开(公告)日：2017-05-11

申请号：US15341707

申请日：2016-11-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shuhei NAGATSUKA ,  Tomokazu YOKOI ,  Naoaki TSUTSUI ,  Kazuaki OHSHIMA ,  Tatsuya ONUKI

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C7/12 ,  H01L27/115 ,  G11C5/06

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/10 ,  G11C7/12 ,  G11C7/18 ,  G11C8/10 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4094 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/30 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582

Abstract: A semiconductor device or a memory device with a reduced area, a large storage capacity, a high-speed operation, or low power consumption is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, a first wiring, a second wiring, a sense amplifier circuit, a decoder, a step-up circuit, a level shifter, and a buffer circuit. The first wiring is electrically connected to the buffer circuit and a second gate electrode of the first transistor. The second wiring is electrically connected to the sense amplifier circuit and the drain electrode of the second transistor. The capacitor is electrically connected to the drain electrode of the first transistor and the source electrode of the second transistor.

公开(公告)号：US20250028379A1

公开(公告)日：2025-01-23

申请号：US18716284

申请日：2022-12-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Masashi FUJITA ,  Kazuaki OHSHIMA

IPC: G06F1/3287 ,  G11C11/4074 ,  G11C11/4096 ,  H01L29/786

Abstract: A novel semiconductor is provided. The semiconductor includes a first component, a second component, and an instruction portion. The first component includes a first memory circuit having a function of storing first setting information in a state where power is supplied, and a second memory circuit having a function of storing the first setting information in a state where power is not supplied. The second component includes a third memory circuit having a function of storing second setting information in a state where power is supplied, and a fourth memory circuit having a function of storing the second setting information in a state where power is not supplied. The instruction portion has a function of controlling whether power is supplied to each of the first component and the second component. Each of the second memory circuit and the fourth memory circuit includes a transistor including a metal oxide in a semiconductor layer where a channel is formed.

公开(公告)号：US20220208794A1

公开(公告)日：2022-06-30

申请号：US17606533

申请日：2020-04-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Kazuaki OHSHIMA ,  Kazuki TSUDA ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/786

Abstract: A semiconductor device with a small characteristic variation due to operating temperature is provided. The semiconductor device includes an odd number of stages of inverter circuits that are circularly connected. The inverter circuit includes a first transistor and a second transistor. A gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, the one of the source and the drain of the first transistor is supplied with a high power supply potential, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to an input terminal in, one of a source and a drain of the second transistor is electrically connected to the output terminal out, and the other of the source and the drain of the second transistor is supplied with a low power supply potential. The first transistor and the second transistor include an oxide semiconductor in a semiconductor layer. The first transistor and the second transistor each include a back gate.

公开(公告)号：US20170186749A1

公开(公告)日：2017-06-29

申请号：US15383274

申请日：2016-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L27/105 ,  H01L27/11 ,  H01L27/108 ,  G06F1/32 ,  H01L23/528 ,  G11C5/06 ,  G11C5/14 ,  H01L27/12 ,  H01L23/522

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C5/06 ,  G11C5/14 ,  G11C7/04 ,  G11C11/401 ,  G11C11/4074 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/1108 ,  H01L27/1207 ,  H01L27/1211 ,  H01L27/1225 ,  H01L29/7851 ,  H01L29/78648 ,  H01L29/7869

Abstract: Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

公开(公告)号：US20160225772A1

公开(公告)日：2016-08-04

申请号：US15007259

申请日：2016-01-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Daigo SHIMADA ,  Tsutomu MURAKAWA

IPC: H01L27/105 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G11C11/401 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN  ( t ) = V 0 ×  - ( t τ ) β ( 1 )

Abstract translation: 可以测量微小电流的半导体器件。 半导体器件包括第一晶体管，第二晶体管，节点和电容器。 第一晶体管包括沟道形成区中的氧化物半导体。 该节点电连接到第二晶体管的栅极和电容器的第一端子。 通过在提供电位V0之后关闭第一晶体管，使节点进入电浮动状态。 随着时间的推移，节点的潜在VFN的变化由公式（1）表示。 在公式（1）中，t是节点进入电浮动状态之后的经过时间，τ是以时间为单位的常数，β是大于或等于0.4且小于等于0.6的常数。 V FN（t）= V 0× - （tτ）β（1）

公开(公告)号：US20250029648A1

公开(公告)日：2025-01-23

申请号：US18715300

申请日：2022-12-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Masashi FUJITA ,  Kazuaki OHSHIMA

IPC: G11C11/405 ,  H10B12/00

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a register. The register includes a flip-flop and a plurality of data retention circuits. The flip-flop includes a first transistor in which a semiconductor layer including a channel formation region is silicon, an input terminal of the flip-flop is electrically connected to each of output terminals of the data retention circuits, and an output terminal of the flip-flop is electrically connected to each of input terminals of the data retention circuits. The data retention circuits include a second transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor, and when the second transistor is in a non-conduction state, the data retention circuits have a function of retaining a potential corresponding to data corresponding to a plurality of tasks. A state control portion rewrites data that the flip-flop has on the basis of data retained in the data retention circuits in accordance with the plurality of tasks executed by a processor core.

公开(公告)号：US20240371306A1

公开(公告)日：2024-11-07

申请号：US18684958

申请日：2022-08-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki OHSHIMA ,  Tatsunori INOUE ,  Yusuke KOUMURA

IPC: G09G3/00 ,  G09G3/32 ,  G09G3/3233

Abstract: A display apparatus with reduced power consumption is provided. The display apparatus includes a display portion including a first region and a second region, a first driver circuit corresponding to the first region, a second driver circuit corresponding to the second region, a first circuit, a second circuit, a first signal generation circuit, and a second signal generation circuit. The first circuit has a function of generating a first image signal corresponding to a first image, and the second circuit has a function of generating a second image signal corresponding to a second image. The second image contains character information. The first signal generation circuit has a function of generating a clock signal with a first frame frequency, and the second signal generation circuit has a function of generating a clock signal with a second frame frequency lower than the first frame frequency. The display apparatus displays the first image on the first region with the first frame frequency when the first image signal is transmitted to the first driver circuit, and displays the second image on the second region with the second frame frequency when the second image signal is transmitted to the second driver circuit.

公开(公告)号：US20220352865A1

公开(公告)日：2022-11-03

申请号：US17765046

申请日：2020-10-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kazuaki OHSHIMA ,  Hitoshi KUNITAKE ,  Yuto YAKUBO ,  Takayuki IKEDA

IPC: H03H7/38 ,  H01L21/822 ,  H01L21/02 ,  H03F3/60 ,  H03F3/19 ,  H01L27/088

Abstract: An amplifier is formed in a wiring layer. A semiconductor device includes a second layer over a first layer with a metal oxide therebetween. The first layer includes a first transistor including a first semiconductor layer containing silicon. The second layer includes an impedance matching circuit, and the impedance matching circuit includes a second transistor including a second semiconductor layer containing gallium. The first transistor forms first coupling capacitance between the first transistor and the metal oxide, and the impedance matching circuit forms second coupling capacitance between the impedance matching circuit and the metal oxide. The impedance matching circuit is electrically connected to the metal oxide through the second coupling capacitance. The metal oxide inhibits the influence of first radiation noise emitted from the impedance matching circuit on the operation of the first transistor.