公开(公告)号：US20240020012A1

公开(公告)日：2024-01-18

申请号：US18203901

申请日：2023-05-31

Applicant: SiFive, Inc.

Inventor： Eric Andrew Gouldey ,  Wesley Waylon Terpstra ,  Andrew Waterman

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: A processor core may include circuitry that fetches a first instruction followed by a second instruction. The first instruction may be configured to cause a first memory request, and the second instruction may be configured to cause a second memory request. The circuitry may determine that the first memory request is a candidate for combination with the second memory request. Responsive to the determination, the circuitry may send an indication, from the processor core via a bus, that the first memory request is a candidate for combination.

公开(公告)号：US20230315649A1

公开(公告)日：2023-10-05

申请号：US18024262

申请日：2021-09-01

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F12/14 ,  G06F21/62 ,  G06F9/30

CPC classification number: G06F12/1458 ,  G06F21/6218 ,  G06F9/30036 ,  G06F2212/1052

Abstract: Systems and methods are disclosed for memory protection for vector operations. For example, a method includes fetching a vector memory instruction using a processor core including a pipeline configured to execute instructions, including constant-stride vector memory instructions; partitioning a vector that is identified by the vector memory instruction into a subvector of a maximum length, greater than one, and one or more additional subvectors with lengths less than or equal to the maximum length; checking, using a memory protection circuit, whether accessing elements of the subvector will cause a memory protection violation; and accessing the elements of the subvector before checking, using the memory protection circuit, whether accessing elements of one of the one or more additional subvectors will cause a memory protection violation.

公开(公告)号：US20240020124A1

公开(公告)日：2024-01-18

申请号：US18345007

申请日：2023-06-30

Applicant: SiFive, Inc.

Inventor： Andrew Waterman ,  Krste Asanovic

IPC: G06F9/30

CPC classification number: G06F9/30101 ,  G06F9/3012

Abstract: Systems and methods are disclosed for supporting multiple vector lengths with a configurable vector register file. For example, an integrated circuit (e.g., a processor) includes a data store configured to store a vector length parameter; a processor core including a vector register, wherein the processor core is configured to: while a first value of the vector length parameter is stored in the data store, store a single architectural register of an instruction set architecture in the vector register; and, while a second value of the vector length parameter is stored in the data store, store multiple architectural registers of the instruction set architecture in respective disjoint portions of the vector register. For example, the integrated circuit may be used to emulate a processor with smaller vector registers for the purpose of migrating a thread to a processor core of the integrated circuit for continued execution.

公开(公告)号：US20230305852A1

公开(公告)日：2023-09-28

申请号：US18017792

申请日：2021-07-23

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/3013

Abstract: Systems and methods are disclosed for register renaming. For example, an integrated circuit is described that includes a first cluster including a first set of physical registers and a first execution resource circuit, wherein the inputs for operations of the first execution resource circuit are of a first data type; a second cluster including a second set of physical registers and a second execution resource circuit, wherein the inputs for operations of the second execution resource circuit are of a second data type that is different than the first data type; and a register renaming circuit configured to: determine a data type prediction for a result of a first instruction that will be stored in a first logical register; and, based on the data type prediction matching the first data type, rename the first logical register to be stored in a physical register of the first set of physical registers.

公开(公告)号：US11687342B2

公开(公告)日：2023-06-27

申请号：US17418933

申请日：2019-12-12

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3802 ,  G06F9/30047 ,  G06F9/321 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3816 ,  G06F9/3861 ,  G06F12/0875 ,  G06F2212/452

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

公开(公告)号：US20210303300A1

公开(公告)日：2021-09-30

申请号：US16856462

申请日：2020-04-23

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.

公开(公告)号：US11048515B2

公开(公告)日：2021-06-29

申请号：US16553839

申请日：2019-08-28

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F12/0875

Abstract: Disclosed herein are systems and method for instruction tightly-coupled memory (iTIM) and instruction cache (iCache) access prediction. A processor may use a predictor to enable access to the iTIM or the iCache and a particular way (a memory structure) based on a location state and program counter value. The predictor may determine whether to stay in an enabled memory structure, move to and enable a different memory structure, or move to and enable both memory structures. Stay and move predictions may be based on whether a memory structure boundary crossing has occurred due to sequential instruction processing, branch or jump instruction processing, branch resolution, and cache miss processing. The program counter and a location state indicator may use feedback and be updated each instruction-fetch cycle to determine which memory structure(s) needs to be enabled for the next instruction fetch.

公开(公告)号：US20240104024A1

公开(公告)日：2024-03-28

申请号：US18475310

申请日：2023-09-27

Applicant: SiFive, Inc.

Inventor： John Ingalls ,  Andrew Waterman

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: Systems and methods are disclosed for atomic memory operations for address translation. For example, an integrated circuit (e.g., a processor) for executing instructions includes a memory system including random access memory; a bus connected to the memory system; and an atomic memory operation circuitry configured to receive a request from the bus to access an entry in a page table stored in the memory system, wherein the request includes an indication of whether an instruction that references an address being translated using the entry is a store instruction; access the entry in the page table; responsive to the indication indicating that the instruction is a store instruction, set a dirty bit of the entry in the page table; and transmit contents of the entry on the bus in response to the request.

公开(公告)号：US11861365B2

公开(公告)日：2024-01-02

申请号：US17306373

申请日：2021-05-03

Applicant: SiFive, Inc.

Inventor： Krste Asanovic ,  Andrew Waterman

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30145 ,  G06F9/3844

Abstract: Systems and methods are disclosed for macro-op fusion. Sequences of macro-ops that include a control-flow instruction are fused into single micro-ops for execution. The fused micro-ops may avoid the use of control-flow instructions, which may improve performance. A fusion predictor may be used to facilitate macro-op fusion.

公开(公告)号：US11797308B2

公开(公告)日：2023-10-24

申请号：US17718258

申请日：2022-04-11

Applicant: SiFive, Inc.

Inventor： Joshua Smith ,  Krste Asanovic ,  Andrew Waterman

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3806 ,  G06F9/30054 ,  G06F9/322 ,  G06F9/3844 ,  G06F9/3867

Abstract: Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor pipeline. For example, a method includes detecting a sequence of instructions fetched by a processor core, wherein the sequence of instructions includes a first instruction, with a result that depends on an immediate field of the first instruction and a program counter value, followed by a second instruction that is an indirect jump instruction; responsive to detection of the sequence of instructions, preventing an indirect jump target predictor circuit from generating a target address prediction for the second instruction; and, responsive to detection of the sequence of instructions, determining a target address for the second instruction before the first instruction is issued to an execution stage of a pipeline of the processor core.