Associative memory circuit
    2.
    发明授权
    Associative memory circuit 失效
    相关记忆电路

    公开(公告)号:US3634833A

    公开(公告)日:1972-01-11

    申请号:US3634833D

    申请日:1970-03-12

    CPC classification number: H03K3/35 G11C11/4116 G11C15/04 H03K3/288

    Abstract: An associative memory circuit suitable for integrated circuit fabrication, using multiemitter transistor logic techniques employs base-to-collector cross-coupled, bistable multivibrators to provide better memory cells with fewer components. In a circuit comprised of a plurality of memory cells, each cell includes means for addressing the cell, means for writing into it, means for reading out of it, and means for indicating whether the information stored therein is equal to other reference information, coupled to various emitters of the multiemitter transistors.

    Abstract translation: 适用于集成电路制造的关联存储器电路使用多发射晶体管逻辑技术采用基极到集电极交叉耦合的双稳态多谐振荡器,以更少的组件提供更好的存储单元。 在由多个存储单元组成的电路中,每个单元包括用于寻址单元的装置,用于写入单元的装置,用于读出单元的装置,用于读出单元的装置,以及用于指示其中存储的信息是否等于其他参考信息的装置, 涉及多发射晶体管的各种发射极。

    Multiphase binary shift register
    3.
    发明授权
    Multiphase binary shift register 失效
    多相二进制移位寄存器

    公开(公告)号:US3619642A

    公开(公告)日:1971-11-09

    申请号:US3619642D

    申请日:1969-11-12

    Inventor: DUNN ROGER S

    CPC classification number: G11C19/28 G11C19/00 G11C19/184

    Abstract: A high stability, binary data, multiphase shift register of at least three phases, stores and shifts ''''N'''' bits of binary information in approximately (N X n)/(n-1) binary switches, where n is the number of phases utilized in the register, and N is the maximum number of bits capable of being stored in the shift register at all times during its operation. The binary switches are connected in series and each is then selectively connected to one of the n phases.

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