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公开(公告)号:US20240214511A1
公开(公告)日:2024-06-27
申请号:US18599324
申请日:2024-03-08
Applicant: Texas Instruments Incorporated
Inventor: Mihir Narendra MODY , Brijesh JADAV , Gang HUA , Niraj NANDAN , Rajasekhar Reddy ALLU , Ankur ANKUR , Mayank MANGLA
CPC classification number: H04N5/2628 , G06T3/40 , G06T7/12 , G06T7/60 , G06T11/00
Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
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公开(公告)号:US20210209719A1
公开(公告)日:2021-07-08
申请号:US16847864
申请日:2020-04-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Niraj NANDAN , Rajat SAGAR , Shashank DABRAL , Anthony LELL , Brijesh JADAV
Abstract: A reconfigurable image processing pipeline includes an image signal processor (ISP), a control processor, and a local memory. ISP processes raw pixel data for a frame based on an image processing parameter and provides lines of processed pixel data to control processor via a first interface. For each region of interest (ROI) in the frame, ISP generates auto-exposure and auto-white balance (2A) statistics based on the lines for the ROI and writes them to the local memory via a second interface. Control processor reads 2A statistics from the local memory, determines the image processing parameter based on them, and provides the image processing parameter to ISP. ISP also generates an integer N bin histogram for control processor, which sums a portion of the N total bins and compares the summed bin count to a lighting transition threshold. The image processing parameter is further based on the comparison.
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公开(公告)号:US20240427717A1
公开(公告)日:2024-12-26
申请号:US18819007
申请日:2024-08-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
Abstract: Systems and methods in which trace data is efficiently managed are provided. An example system includes a memory, a first interface, and a processing resource communicably coupled to the first interface and to the memory. The processing resource includes a buffer, and a first controller to transmit a set of data from the buffer with associated trace information for the set of data to the memory. A second controller transmits the set of data with the associated trace information from the memory to a second interface.
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公开(公告)号:US20230291864A1
公开(公告)日:2023-09-14
申请号:US17690829
申请日:2022-03-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY , Brijesh JADAV , Gang HUA , Niraj NANDAN , Rajasekhar Reddy ALLU , Ankur ANKUR , Mayank MANGLA
CPC classification number: H04N5/2628 , G06T3/40 , G06T7/12 , G06T7/60 , G06T11/00
Abstract: A technique for determining regions and block sizes for configuring a perspective transformation engine including determining a set of scale ratios for images captured by a camera, generating a scale ratio image based on the set of scale ratios, determining a set of boundary ranges for the scale ratio image, generating a binary scale ratio image using the set of scale ratios of the scale ratio image, determining a set of regions based on the set of boundary ranges for the binary scale ratio image, determining a block size for each region of the determined set of regions, and outputting the determined set of regions and the determined block sizes.
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公开(公告)号:US20230267084A1
公开(公告)日:2023-08-24
申请号:US17677638
申请日:2022-02-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Mihir Narendra MODY, JR. , Ankur ANKUR , Vivek Vilas DHANDE , Kedar Satish CHITNIS , Niraj NANDAN , Brijesh JADAV , Shyam JAGANNATHAN , Prithvi Shankar YEYYADI ANANTHA , Santhanakrishnan Narayanan NARAYANAN
CPC classification number: G06F13/28 , G06F13/1673 , G06F13/4221 , G06F15/7807 , G06F9/4881
Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.
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