公开(公告)号：US20240413114A1

公开(公告)日：2024-12-12

申请号：US18810928

申请日：2024-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Salvatore Frank PAVONE ,  Maricel Fabia ESCAÑO ,  Rafael Jose Lizares GUEVARA

IPC: H01L23/00

Abstract: In examples, a semiconductor package comprises a semiconductor die having an active surface; a conductive layer coupled to the active surface; and a polyimide layer coupled to the conductive layer. The package also comprises a conductive pillar coupled to the conductive layer and to the polyimide layer; a flux adhesive material coupled to the conductive pillar; and a solder layer coupled to the flux adhesive material. The package further includes a conductive terminal coupled to the solder layer and exposed to a surface of the package, the active surface of the semiconductor die facing the conductive terminal.

公开(公告)号：US20230274978A1

公开(公告)日：2023-08-31

申请号：US17682617

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael Todd WYANT ,  Joseph LIU ,  Christopher Daniel MANACK

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L21/78 ,  H01L22/12 ,  H01L23/544 ,  H01L23/31

Abstract: In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer by way of the opening in the photoresist layer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape from device sides of the first and second semiconductor dies, wherein removing the tape includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound, the conductive member exposed to an exterior surface of the mold compound.

公开(公告)号：US20220059423A1

公开(公告)日：2022-02-24

申请号：US17001429

申请日：2020-08-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Qiao CHEN

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US20190109109A1

公开(公告)日：2019-04-11

申请号：US16038598

申请日：2018-07-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila DADVAND ,  Christopher Daniel MANACK ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1

公开(公告)号：US20240234231A1

公开(公告)日：2024-07-11

申请号：US18617517

申请日：2024-03-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Qiao CHEN

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/315 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/07025 ,  H01L2924/19104

Abstract: In examples, a semiconductor device comprises a semiconductor package including a mold compound covering a semiconductor die. The semiconductor package has a surface and a cavity formed in the surface. The semiconductor device comprises an electronic device positioned within the cavity, the electronic device coupled to the semiconductor die via a conductive terminal extending through the mold compound.

公开(公告)号：US20230065075A1

公开(公告)日：2023-03-02

申请号：US17463047

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qiao CHEN ,  Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Patrick Francis THOMPSON ,  Jonathan Andrew MONTOYA ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.

公开(公告)号：US20220173062A1

公开(公告)日：2022-06-02

申请号：US17672463

申请日：2022-02-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila DADVAND ,  Christopher Daniel MANACK ,  Salvatore Frank PAVONE

IPC: H01L23/00

Abstract: A structure for a semiconductor device includes a copper (Cu) layer and a first nickel (Ni) alloy layer with a Ni grain size a1. The structure also includes a second Ni alloy layer with a Ni grain size a2, wherein a1

公开(公告)号：US20210384150A1

公开(公告)日：2021-12-09

申请号：US16950708

申请日：2020-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

公开(公告)号：US20210193600A1

公开(公告)日：2021-06-24

申请号：US16721546

申请日：2019-12-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Nazila DADVAND ,  Salvatore Frank PAVONE ,  Patrick Francis THOMPSON

IPC: H01L23/00

Abstract: In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

公开(公告)号：US20250029943A1

公开(公告)日：2025-01-23

申请号：US18909550

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vivek Swaminathan SRIDHARAN ,  Christopher Daniel MANACK ,  Joseph LIU

IPC: H01L23/00

Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.