SUBSTRATE CONTACT INTEGRATION IN GALLIUM NITRIDE DEVICES

    公开(公告)号:US20250006593A1

    公开(公告)日:2025-01-02

    申请号:US18345939

    申请日:2023-06-30

    Abstract: A microelectronic device includes a semiconductor substrate with a III-N semiconductor layer over the semiconductor substrate. A substrate via opening extending through the III-N semiconductor layer and a substrate contact pad in the substrate via opening, contacting the semiconductor substrate provide a substrate contact. The microelectronic device also includes an inter-level dielectric layer with a planar surface over the substrate contact. The microelectronic device further includes an interconnect metal level over the inter-level dielectric layer. The substrate via opening is formed through the III-N semiconductor layer to expose the semiconductor substrate. The substrate contact pad is formed over the III-N semiconductor layer, extending into the substrate via opening and making contact with the semiconductor substrate, to form the substrate contact. The ILD layer is formed over the III-N semiconductor layer and the substrate contact pad, so that the ILD layer has a planar surface over the substrate via opening.

    Transistor with source field plates and non-overlapping gate runner layers

    公开(公告)号:US10263085B2

    公开(公告)日:2019-04-16

    申请号:US15415995

    申请日:2017-01-26

    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

    Transistor with source field plates and non-overlapping gate runner layers

    公开(公告)号:US10903320B2

    公开(公告)日:2021-01-26

    申请号:US16383857

    申请日:2019-04-15

    Abstract: A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

Patent Agency Ranking