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    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
    1.
    发明授权
    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter 有权

    公开(公告)号：US10727852B2

    公开(公告)日：2020-07-28

    申请号：US16555265

    申请日：2019-08-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

    IPC: H03K5/00 ,  H03M1/08 ,  H03K5/24

    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

    Frequency detector and oscillator circuit
    4.
    发明授权
    Frequency detector and oscillator circuit 有权

    公开(公告)号：US09602084B2

    公开(公告)日：2017-03-21

    申请号：US14966616

    申请日：2015-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Subramanian Jagdish Narayan ,  Dipankar Mandal ,  Janakiraman Seetharaman ,  Kiran Godbole

    IPC: G01R23/02 ,  H03K3/037 ,  G01R19/165

    CPC classification number: H03K3/037 ,  G01R19/1659 ,  H03K3/0231

    Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
    5.
    发明授权
    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter 有权

    公开(公告)号：US10447290B2

    公开(公告)日：2019-10-15

    申请号：US15837040

    申请日：2017-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

    IPC: H03K5/00 ,  H03M1/08 ,  H03K5/24

    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

    FREQUENCY DETECTOR AND OSCILLATOR CIRCUIT
    6.
    发明申请
    FREQUENCY DETECTOR AND OSCILLATOR CIRCUIT 有权
    频率检测器和振荡器电路

    公开(公告)号：US20160308516A1

    公开(公告)日：2016-10-20

    申请号：US14966616

    申请日：2015-12-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Subramanian Jagdish Narayan ,  Dipankar Mandal ,  Janakiraman Seetharaman ,  Kiran Godbole

    IPC: H03K3/037 ,  G01R19/165

    CPC classification number: H03K3/037 ,  G01R19/1659 ,  H03K3/0231

    Abstract: Frequency detector and oscillator circuits are disclosed. Example frequency detector and oscillator circuits disclosed herein include a current approximation circuit coupled to an external clock operating at a target frequency. In some examples, the current approximation circuit is configured to determine a magnitude of a first current to charge a capacitor to reach a reference voltage during a first set of clock cycles generated by the external clock. In some examples, the current approximation circuit is further configured to generate an output current based on the magnitude of the first current and to use the output current to produce a comparator output. In some examples, the frequency detector and oscillator circuits further include a latching circuit coupled to receive the comparator output from the current approximation circuit. In some such examples, the latching circuit is configured to generate oscillating signals at the target frequency based on the comparator output.

    Abstract translation: 公开了频率检测器和振荡器电路。 本文公开的示例性频率检测器和振荡器电路包括耦合到以目标频率工作的外部时钟的电流近似电路。 在一些示例中，电流近似电路被配置为在由外部时钟产生的第一组时钟周期期间确定用于对电容器充电以达到参考电压的第一电流的幅度。 在一些示例中，电流近似电路还被配置为基于第一电流的幅度产生输出电流并且使用输出电流来产生比较器输出。 在一些示例中，频率检测器和振荡器电路还包括耦合以从电流近似电路接收比较器输出的锁存电路。 在一些这样的示例中，锁存电路被配置为基于比较器输出以目标频率产生振荡信号。

    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter
    8.
    发明授权
    Reduced noise dynamic comparator for a successive approximation register analog-to-digital converter 有权

    公开(公告)号：US11095300B2

    公开(公告)日：2021-08-17

    申请号：US16904604

    申请日：2020-06-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

    IPC: H03K5/24 ,  H03M1/08

    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

    REDUCED NOISE DYNAMIC COMPARATOR FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER
    9.
    发明申请
    REDUCED NOISE DYNAMIC COMPARATOR FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER 审中-公开

    公开(公告)号：US20200321970A1

    公开(公告)日：2020-10-08

    申请号：US16904604

    申请日：2020-06-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sovan Ghosh ,  Amal Kumar Kundu ,  Janakiraman Seetharaman

    IPC: H03M1/08 ,  H03K5/24

    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.

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