公开(公告)号：US20240211254A1

公开(公告)日：2024-06-27

申请号：US18594461

申请日：2024-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30112 ,  G06F9/3893

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US11977892B2

公开(公告)日：2024-05-07

申请号：US17748954

申请日：2022-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0875 ,  G06F12/0897 ,  G06F5/06

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F5/06 ,  G06F9/30043 ,  G06F9/3822 ,  G06F11/10 ,  G06F2205/067 ,  G06F2212/452 ,  G06F2212/60

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

公开(公告)号：US11922166B2

公开(公告)日：2024-03-05

申请号：US18097552

申请日：2023-01-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30021 ,  G06F9/30112 ,  G06F9/3893

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US11556338B2

公开(公告)日：2023-01-17

申请号：US16852690

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David Anderson ,  Duc Quang Bui ,  Mujibur Rahman ,  Joseph Raymond Michael Zbiciak ,  Eric Biscondi ,  Peter Dent ,  Jelena Milanovic ,  Ashish Shrivastava

IPC: G06F9/30 ,  G06F9/38

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

公开(公告)号：US20220283809A1

公开(公告)日：2022-09-08

申请号：US17748954

申请日：2022-05-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F11/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

公开(公告)号：US11347510B2

公开(公告)日：2022-05-31

申请号：US16861347

申请日：2020-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F11/10 ,  G06F9/32 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F5/06

Abstract: A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

公开(公告)号：US11119776B2

公开(公告)日：2021-09-14

申请号：US16825348

申请日：2020-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/34 ,  G06F12/08 ,  G06F11/00 ,  G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F12/0831 ,  G06F12/1027 ,  G06F12/02 ,  G06F12/0862

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US10942741B2

公开(公告)日：2021-03-09

申请号：US16282508

申请日：2019-02-22

Applicant: Texas Instruments Incorporated

Inventor： Jonathan (Son) Hung Tran ,  Joseph Raymond Michael Zbiciak

IPC: G06F7/78 ,  G06F9/302 ,  G06F17/16 ,  G06F9/30 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00 ,  G06F9/345

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors. Local storage on the streaming engine is organized as sectors based on the number of rows in the matrix to allow overlapping transposition processing and to minimize memory accesses.

公开(公告)号：US20200285470A1

公开(公告)日：2020-09-10

申请号：US16827875

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Raymond Michael Zbiciak ,  Timothy David Anderson ,  Jonathan (Son) Hung Tran ,  Kai Chirca ,  Daniel Wu ,  Abhijeet Ashok Chachad ,  David M. Thompson

IPC: G06F9/30 ,  G06F9/345 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0897 ,  G06F11/10 ,  G06F11/00 ,  G06F12/0862 ,  G06F12/1036

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache preload operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

公开(公告)号：US20190187986A1

公开(公告)日：2019-06-20

申请号：US16282526

申请日：2019-02-22

Applicant: Texas Instruments Incorporated

Inventor： Jonathan (Son) Hung Tran ,  Joseph Raymond Michael Zbiciak

IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F11/00

CPC classification number: G06F9/3016 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3822 ,  G06F9/383 ,  G06F9/3867 ,  G06F11/00 ,  G06F11/10 ,  G06F11/1048 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452 ,  G06F2212/60

Abstract: Software instructions are executed on a processor within a computer system to configure a steaming engine to operate in either a linear mode or a transpose mode. A stream of addresses is generated using an address generator, in which the stream of addresses includes consecutive nested loop iterations for at least a first loop and a second loop. While in the linear mode, the first loop is treated as an inner loop. While in the transpose mode, the second loop is treated as the inner loop. A matrix can be fetched from memory in the linear mode to provide row-wise vectors. A matrix can be fetched from the memory in the transpose mode to provide column wise vectors.