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    CROSSTALK REDUCTION IN RECEIVER INDUCTIVE LOOP USING CAPTURING LOOP IN TRANSMITTING INDUCTIVE LOOP
    1.
    发明申请
    CROSSTALK REDUCTION IN RECEIVER INDUCTIVE LOOP USING CAPTURING LOOP IN TRANSMITTING INDUCTIVE LOOP 有权

    公开(公告)号：US20210036735A1

    公开(公告)日：2021-02-04

    申请号：US17076275

    申请日：2020-10-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kumar Anurag SHRIVASTAVA

    IPC: H04B3/32 ,  H04B1/10 ,  H04L25/02

    Abstract: An inductively coupled multi-channel digital isolator where the transmitter and receiver inductive loops of a given channel are coplanar. In the case where two adjacent channels flow data in opposite directions, the receiver inductive loops of a given channel include a large, generally conventional loop portion and a small loop portion that is located inside the transmitter inductive loops of the adjacent channels. The sizes of the small loop portion and the conventional loop portion are generally in the ratio of the magnetic flux in the conventional loop portion to the magnetic flux in the transmitter inductive loop. This size relationship results in the voltage of the small loop portion being very close but opposite in sign to the voltage in the conventional loop portion. As a result, there is minimal crosstalk from the transmitter inductive loop of one channel to the receiver inductive loop of the adjacent channel.

    ISOLATED DIGITAL INPUT RECEIVER WITH SINK AND SOURCE MODE SUPPORT
    3.
    发明申请
    ISOLATED DIGITAL INPUT RECEIVER WITH SINK AND SOURCE MODE SUPPORT 有权

    公开(公告)号：US20240380397A1

    公开(公告)日：2024-11-14

    申请号：US18657273

    申请日：2024-05-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Himanth MUDDA ,  Tarunvir SINGH ,  Anant Shankar KAMATH ,  Kumar Anurag SHRIVASTAVA

    IPC: H03K17/51 ,  H03K19/20

    Abstract: In some examples, a circuit includes a sink/source mode detector configured to compare a voltage provided at the first I/O terminal of the circuit to a first reference signal; determine, responsive to the voltage provided at the first I/O terminal exceeding the first reference signal, that the circuit is in a source mode; determine, responsive to the voltage provided at the first I/O terminal not exceeding the first reference signal, that the circuit is in a sink mode; responsive to determining that the circuit is in the source mode and an input signal of the circuit has a value less than a second reference signal, control a first switch to form a first current path between a voltage supply terminal and the first I/O terminal of the circuit; and responsive to determining that the circuit is in the sink mode and the input signal has a value greater than the second reference signal, control a second switch to form a second current path between a ground terminal and the first I/O terminal of the circuit.

    ISOLATOR CIRCUIT
    4.
    发明公开
    ISOLATOR CIRCUIT 审中-公开

    公开(公告)号：US20240305274A1

    公开(公告)日：2024-09-12

    申请号：US18179482

    申请日：2023-03-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kumar Anurag SHRIVASTAVA

    IPC: H03H11/02 ,  H03K5/01 ,  H03K19/21

    CPC classification number: H03H11/02 ,  H03K5/01 ,  H03K19/21 ,  H03K2005/00013

    Abstract: In some examples, an apparatus includes an isolating transformer and a grounding circuit. The isolating transformer has first and second coils separated by an isolation barrier, the first coil having first and second terminals. The grounding circuit is coupled to the first and second terminals. The grounding circuit is configured to couple the first and second terminals to a ground terminal during a first time period. The grounding circuit is also configured to decouple the first and second terminals from the ground terminal during a second time period.

    INTEGRATED CIRCUIT WITH BONDWIRE FAULT DETECTION CIRUIT
    6.
    发明公开
    INTEGRATED CIRCUIT WITH BONDWIRE FAULT DETECTION CIRUIT 审中-公开

    公开(公告)号：US20240195412A1

    公开(公告)日：2024-06-13

    申请号：US18194289

    申请日：2023-03-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kashyap BAROT ,  Kumar Anurag SHRIVASTAVA ,  Sreeram Nasum S

    IPC: H03K17/687

    CPC classification number: H03K17/6874

    Abstract: A circuit includes a switch and a switch controller. The switch has a first terminal coupled to a voltage supply terminal, a second terminal coupled to a ground terminal and to a first bondwire terminal. The switch controller includes: a first resistor, a second resistor, a capacitor, and a buffer circuit. The first resistor has a first terminal coupled to a second bondwire terminal. The second resistor has a first terminal coupled to the voltage supply terminal and has a second terminal coupled to a second terminal of the first resistor. The capacitor has a first terminal coupled to the ground terminal and to the first bondwire terminal and has a second terminal coupled to second terminals of the first and second resistors. The buffer circuit has a terminal coupled to the second terminal of the capacitor and has an output terminal coupled to the control terminal of the switch.

    CENTER-TAPPED ISOLATION TRANSFORMER
    7.
    发明公开
    CENTER-TAPPED ISOLATION TRANSFORMER 审中-公开

    公开(公告)号：US20240105382A1

    公开(公告)日：2024-03-28

    申请号：US17954735

    申请日：2022-09-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kashyap BAROT ,  Sreeram S ,  Kumar Anurag SHRIVASTAVA ,  Viresh CHINCHANSURE

    IPC: H01F27/30 ,  H01F27/32

    CPC classification number: H01F27/303 ,  H01F27/306 ,  H01F27/324

    Abstract: A transformer includes a substrate and a first metal layer having a first inductor having a first center tap. A second metal layer includes a second inductor having a second center tap, and the second metal layer includes a bond pad. A third metal layer includes a first conductor electrically connecting the bond pad to the first center tap, and the third metal layer includes a second conductor electrically connecting the bond pad and the first center tap. The third metal layer is situated between the substrate and the first metal layer, and the first metal layer is situated between the third metal layer and the second metal layer.

    ARCHITECTURE FOR RESOLUTION OF DATA AND REFRESH-PATH CONFLICT FOR LOW-POWER DIGITAL ISOLATOR
    10.
    发明申请
    ARCHITECTURE FOR RESOLUTION OF DATA AND REFRESH-PATH CONFLICT FOR LOW-POWER DIGITAL ISOLATOR 审中-公开

    公开(公告)号：US20200279602A1

    公开(公告)日：2020-09-03

    申请号：US16793447

    申请日：2020-02-18

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sreeram Subramanyam NASUM ,  Niranjan SHANKAR ,  Kumar Anurag SHRIVASTAVA ,  Kashyap BAROT

    IPC: G11C11/406 ,  G11C11/409 ,  G11C7/22 ,  G11C7/10

    Abstract: An encoding and transmitting system for a digital isolator system includes a transmitter for transmitting combined edge indicator signals through an isolation barrier, an encoder for generating the combined edge indicator signals based on first and second signals, a refresh clock generator for generating a refresh clock signal based on the first signal, and a refresh edge generator for masking at least a portion of the refresh clock signal, such that the portion of the refresh clock signal is not reflected in the second signal. The isolation barrier of the digital isolator system may be a capacitive isolation barrier for galvanically isolating a receiver from the transmitter. If desired, the refresh edge generator may include a refresh mask generator, one or more logic gates, and a glitch filter. A method of operating a digital isolator system is also described.

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