公开(公告)号：US11996830B2

公开(公告)日：2024-05-28

申请号：US17514968

申请日：2021-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kushal D. Murthy ,  Subrato Roy ,  Dilip Kumar Jain ,  Abhijeet Gopal Godbole

IPC: H03K17/08 ,  G01R19/165 ,  G05F3/18 ,  H02H3/18 ,  H03K17/0812 ,  H03K17/687

CPC classification number: H03K17/08122 ,  G01R19/16538 ,  G05F3/18 ,  H02H3/18 ,  H03K17/687

Abstract: One example described herein includes a power switch control system. The system includes a first monitoring terminal coupled to a first terminal of a power transistor and a second monitoring terminal coupled to a second terminal of the power transistor. The power transistor and the power switch control system can form an ideal diode between the first monitoring terminal arranged as an anode and the second monitoring terminal arranged as a cathode. The system further includes a reverse current controller coupled to the first monitoring terminal and the second monitoring terminal and is configured to control activation of the power transistor to conduct a reverse current from the second monitoring terminal to the first monitoring terminal in response to a reverse voltage arranged as a cathode voltage at the second monitoring terminal being greater than an anode voltage at the first monitoring terminal.

公开(公告)号：US10297334B2

公开(公告)日：2019-05-21

申请号：US15597820

申请日：2017-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindita Borah ,  Muthusubramanian Venkateswaran ,  Kushal D. Murthy ,  Vikram Gakhar ,  Preetam Tadeparthy

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

公开(公告)号：US12199607B2

公开(公告)日：2025-01-14

申请号：US18103753

申请日：2023-01-31

Applicant: Texas Instruments Incorporated

Inventor： Orlando Lazaro ,  Henry Litzmann Edwards ,  Andres Arturo Blanco ,  Kushal D. Murthy ,  Ankur Chauhan

IPC: H03K3/011 ,  H01L27/02 ,  H03K17/687

Abstract: The present disclosure introduces integrated circuits and related manufacturing methods, wherein each integrated circuit includes an electronic device and a thermoelectric circuit. The electronic device is formed in and/or over a semiconductor substrate. The thermoelectric circuit includes thermopiles formed in and/or over the semiconductor substrate and electrically connected in series. The thermoelectric circuit is configured to modulate operation of the electronic device in response to a potential produced by the plurality of thermopiles.

公开(公告)号：US20240258999A1

公开(公告)日：2024-08-01

申请号：US18103753

申请日：2023-01-31

Applicant: Texas Instruments Incorporated

Inventor： Orlando Lazaro ,  Henry Litzmann Edwards ,  Andres Arturo Blanco ,  Kushal D. Murthy ,  Ankur Chauhan

IPC: H03K3/011 ,  H01L27/02 ,  H03K17/687

CPC classification number: H03K3/011 ,  H01L27/0251 ,  H03K17/687

Abstract: The present disclosure introduces integrated circuits and related manufacturing methods, wherein each integrated circuit includes an electronic device and a thermoelectric circuit. The electronic device is formed in and/or over a semiconductor substrate. The thermoelectric circuit includes thermopiles formed in and/or over the semiconductor substrate and electrically connected in series. The thermoelectric circuit is configured to modulate operation of the electronic device in response to a potential produced by the plurality of thermopiles.

公开(公告)号：US11243235B2

公开(公告)日：2022-02-08

申请号：US16230564

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Ramachandran ,  Kushal D. Murthy ,  Aalok Dyuti Saha

IPC: G01R19/165 ,  G01R19/155

Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.

公开(公告)号：US10177644B1

公开(公告)日：2019-01-08

申请号：US15729004

申请日：2017-10-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kushal D. Murthy ,  Vikram Gakhar ,  Muthusubramanian Venkateswaran ,  Preetam Tadeparthy

IPC: H02M3/158 ,  H02M1/08 ,  G01R29/02 ,  G01R19/12 ,  H02M1/00

Abstract: A voltage converter includes a high side power transistor coupled to an input voltage node and a low side power transistor coupled to the high side power transistor at a switch node. The switch node is configured to be coupled to an inductor. A slope detector circuit is configured to receive a signal indicative of a current through the inductor. The inductor current is a triangular waveform comprising a ramp-up phase and a ramp-down phase. The slope detector circuit also is configured to generate an output signal encoding when the inductor current is ramping up and when the inductor current is ramping down.

公开(公告)号：US20170234926A1

公开(公告)日：2017-08-17

申请号：US15042132

申请日：2016-02-11

Applicant: Texas Instruments Incorporated

Inventor： Kushal D. Murthy ,  Manish Parmar ,  Preetam Tadeparthy ,  Muthusubramanian Venkateswaran

IPC: G01R31/3177 ,  H01L21/66 ,  H03K19/0948 ,  G01R31/317 ,  G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2884 ,  G01R31/31723 ,  H01L22/14 ,  H01L22/34 ,  H03K19/0948

Abstract: An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic may be configured to selectively couple a signal received on a second external pin of the IC either via the buffer to the first external pin of the IC in order to calibrate the buffer.