-
公开(公告)号：US20180351667A1
公开(公告)日：2018-12-06
申请号：US16058007
申请日：2018-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun DUSAD , Nagarajan VISWANATHAN
IPC: H04B17/336 , H04L1/24 , H04B17/309 , H04L25/02
CPC classification number: H04B17/336 , H04B17/309 , H04L1/244 , H04L25/0202 , H04L25/0226
Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.
-
公开(公告)号：US20220239304A1
公开(公告)日：2022-07-28
申请号：US17538746
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
Inventor： Karthikeyan GUNASEKARAN , Snehasish ROYCHOWDHURY , Rakesh MANJUNATH , Aswath V S , Sthanunathan RAMAKRISHNAN , Sarma Sudareswara GUNTURI , Rahul SHARMA , Jagannathan VENKATARAMAN , Nagarajan VISWANATHAN
Abstract: A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.
-
公开(公告)号：US20230082872A1
公开(公告)日：2023-03-16
申请号：US17589533
申请日：2022-01-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nagarajan VISWANATHAN , Himanshu VARSHNEY , Vinam ARORA , Charls BABU , Srinivas Kumar NARU
Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
-
公开(公告)号：US20250055473A1
公开(公告)日：2025-02-13
申请号：US18931734
申请日：2024-10-30
Applicant: Texas Instruments Incorporated
Inventor： Nagarajan VISWANATHAN , Himanshu VARSHNEY , Vinam ARORA , Charls BABU , Srinivas Kumar NARU
Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
-
Patent Agency Ranking
公开(公告)号：US20160315629A1
公开(公告)日：2016-10-27
申请号：US14871373
申请日：2015-09-30
Applicant: Texas Instruments Incorporated
CPC classification number: H03M1/0609 , H03M1/203 , H03M1/361
Abstract: In described examples, an analog to digital converter (ADC) includes a main ADC and a reference ADC. The main ADC generates a zone information signal and a digital output in response to an input signal. The reference ADC receives a plurality of reference voltages from the main ADC. The plurality of reference voltages includes a first reference voltage and a second reference voltage. The reference ADC generates a reference output in response to the input signal, the first reference voltage and the second reference voltage. A subtractor generates an error signal in response to the digital output and the reference output. A logic block generates one of a first offset correction signal, a second offset correction signal and a gain mismatch signal in response to the zone information signal, the error signal and the reference output.
Abstract translation: 在所描述的示例中，模数转换器（ADC）包括主ADC和参考ADC。 主ADC响应于输入信号产生区域信息信号和数字输出。 参考ADC从主ADC接收多个参考电压。 多个参考电压包括第一参考电压和第二参考电压。 参考ADC根据输入信号，第一参考电压和第二参考电压产生参考输出。 减法器响应于数字输出和参考输出产生一个误差信号。 响应于区域信息信号，误差信号和参考输出，逻辑块产生第一偏移校正信号，第二偏移校正信号和增益失配信号中的一个。
-
公开(公告)号：US20230412186A1
公开(公告)日：2023-12-21
申请号：US18461152
申请日：2023-09-05
Applicant: Texas Instruments Incorporated
Inventor： Nagarajan VISWANATHAN , Himanshu VARSHNEY , Vinam ARORA , Charls BABU , Srinivas Kumar NARU
CPC classification number: H03M1/502 , H03M1/1009 , H03M1/362
Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
-
公开(公告)号：US20200327950A1
公开(公告)日：2020-10-15
申请号：US16916911
申请日：2020-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind GANESAN , Jaiganesh BALAKRISHNAN , Nagarajan VISWANATHAN , Yeswanth GUNTUPALLI , Ajai PAULOSE , Mathews JOHN , Jagannathan VENKATARAMAN , Neeraj SHRIVASTAVA
Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
-
公开(公告)号：US20200152284A1
公开(公告)日：2020-05-14
申请号：US16235698
申请日：2018-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind GANESAN , Jaiganesh BALAKRISHNAN , Nagarajan VISWANATHAN , Yeswanth GUNTUPALLI , Ajai PAULOSE , Mathews JOHN , Jagannathan VENKATARAMAN , Neeraj SHRIVASTAVA
Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
-
公开(公告)号：US20180191472A1
公开(公告)日：2018-07-05
申请号：US15395783
申请日：2016-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Shagun DUSAD , Nagarajan VISWANATHAN
IPC: H04L5/00 , H04B17/336
CPC classification number: H04B17/336 , H04B17/309 , H04L1/244 , H04L25/0202
Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.
-
-
-
-
-
-
-
-
Search Results
9
records
(took 0.022 seconds)
