中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.015 seconds)

    LOW COST TRANSISTORS
    1.
    发明申请
    LOW COST TRANSISTORS 有权
    低成本晶体管

    公开(公告)号：US20140183631A1

    公开(公告)日：2014-07-03

    申请号：US14101442

    申请日：2013-12-10

    Applicant: Texas Instruments Incorporated

    Inventor： Pinghai HAO ,  Sameer PENDHARKAR

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

    Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。

    LOW COST TRANSISTORS
    2.
    发明申请
    LOW COST TRANSISTORS 审中-公开
    低成本晶体管

    公开(公告)号：US20150325578A1

    公开(公告)日：2015-11-12

    申请号：US14803678

    申请日：2015-07-20

    Applicant: Texas Instruments Incorporated

    Inventor： Pinghai HAO ,  Sameer PENDHARKAR

    IPC: H01L27/092 ,  H01L27/088 ,  H01L29/10 ,  H01L29/36 ,  H01L29/78

    CPC classification number: H01L27/092 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7835

    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

    Abstract translation: 包含模拟MOS晶体管的集成电路具有用于阱的注入掩模，该掩模从栅极边缘处的两个稀释区域阻挡良好的掺杂剂，但是将沟道区域暴露于阱掺杂剂。 热驱动步骤将注入的阱掺杂物扩散到两个稀释区域上以在两个稀释区域中形成具有较低掺杂密度的连续阱。 通过使用栅极作为阻挡层将源极/漏极掺杂剂注入邻近栅极的衬底中，形成栅/漏区邻近并且使其重叠，随后使衬底退火，使得注入的源极/漏极掺杂剂提供期望的程度 栅极下的源极/漏极区的叠加。 漏极延伸掺杂剂和卤素掺杂剂不会被注入到与栅极相邻的衬底中。

    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN
    5.
    发明申请
    HIGH VOLTAGE TRANSISTOR USING DILUTED DRAIN 有权
    使用稀释漏水的高压晶体管

    公开(公告)号：US20130157429A1

    公开(公告)日：2013-06-20

    申请号：US13765054

    申请日：2013-02-12

    Applicant: Texas Instruments Incorporated

    Inventor： Pinghai HAO ,  Sameer PENDHARKAR ,  Binghua HU ,  Qingfeng WANG

    IPC: H01L21/8234

    CPC classification number: H01L29/0847 ,  H01L21/266 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/66659 ,  H01L29/7835

    Abstract: An integrated circuit containing an extended drain MOS transistor may be formed by forming a drift region implant mask with mask fingers abutting a channel region and extending to the source/channel active area, but not extending to a drain contact active area. Dopants implanted through the exposed fingers form lateral doping striations in the substrate under the mask fingers. An average doping density of the drift region under the gate is at least 25 percent less than an average doping density of the drift region at the drain contact active area. In one embodiment, the dopants diffuse laterally to form a continuous drift region. In another embodiment, substrate material between lateral doping striations remains an opposite conductivity type from the lateral doping striations.

    Abstract translation: 包含扩展漏极MOS晶体管的集成电路可以通过形成具有掩模手指的沟道区域的漂移区域注入掩模来形成，并且延伸到源极/沟道有源区，但不延伸到漏极接触有源区。 通过暴露的指状物注入的掺杂剂在掩模指下面的衬底中形成横向掺杂条纹。 栅极下方的漂移区域的平均掺杂密度比漏极接触有效面积处的漂移区域的平均掺杂密度小至少25％。 在一个实施例中，掺杂剂横向漫射以形成连续漂移区域。 在另一个实施例中，横向掺杂条纹之间的衬底材料与横向掺杂条纹保持相反的导电类型。

    SINGLE PHOTOMASK HIGH PRECISION THIN FILM RESISTOR
    10.
    发明申请
    SINGLE PHOTOMASK HIGH PRECISION THIN FILM RESISTOR 审中-公开
    单光电高精密薄膜电阻器

    公开(公告)号：US20160197135A1

    公开(公告)日：2016-07-07

    申请号：US15055959

    申请日：2016-02-29

    Applicant: Texas Instruments Incorporated

    Inventor： Pinghai HAO ,  Fuchao WANG ,  Duofeng YUE

    IPC: H01L49/02

    CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/06 ,  H01C17/075 ,  Y10T29/435

    Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

    Abstract translation: 集成电路包括薄膜电阻器，其中薄膜电阻体的主体设置在集成电路中的互连系统中的下介电层上。 薄膜电阻器的头部设置在电介质上，电极是下电介质层中的互连元件，其提供与薄膜电阻器的底表面的电连接。 电极的顶表面与下介电层的顶表面基本共面。 薄膜电阻的顶表面没有电气连接。 上电介质层设置在薄膜电阻器的上方。

Patent Agency Ranking