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公开(公告)号:US12266596B2
公开(公告)日:2025-04-01
申请号:US17227722
申请日:2021-04-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rajen Manicon Murugan , Yiqi Tang
IPC: H01L23/498 , H01L21/48 , H02M1/00
Abstract: A semiconductor device includes a die with a power converter module. The power converter module includes an output port and a return port. The semiconductor device also includes a connection assembly that includes pads configured to be coupled to circuit components of a printed circuit board (PCB). The connection assembly also includes a first layer patterned to include a first trace that is coupled to one of the output port and the return port and a second trace that is coupled to the other of the output port and return port. A second layer of the connection assembly is patterned to provide a first via between the first trace and a third layer and a second via between the first trace and the third layer. The third layer is patterned to provide a portion of a first conductive path and a portion of a second conductive path.
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公开(公告)号:US11901271B2
公开(公告)日:2024-02-13
申请号:US18148627
申请日:2022-12-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yiqi Tang , Liang Wan , William Todd Harrison , Manu Joseph Prakuzhy , Rajen Manicon Murugan
IPC: H01L23/495 , H02M3/158 , H01L23/00
CPC classification number: H01L23/49575 , H01L23/49524 , H01L23/49562 , H01L24/32 , H02M3/158 , H01L2224/32245
Abstract: In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
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公开(公告)号:US11837775B2
公开(公告)日:2023-12-05
申请号:US17539110
申请日:2021-11-30
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan , Juan Alejandro Herbsommer
CPC classification number: H01Q1/2283 , H01L23/3114 , H01L23/66 , H05K1/0237 , H01L2223/6677
Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.
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公开(公告)号:US20230198170A1
公开(公告)日:2023-06-22
申请号:US18169682
申请日:2023-02-15
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan
CPC classification number: H01Q23/00 , H01L23/66 , H01Q1/2283
Abstract: An AIP includes a package substrate including a top layer including a top metal layer including a first antenna type and a second antenna type, and a bottom layer including a bottom dielectric and a metal layer including a first and second contact pad and filled vias, and an IC embedded therein. Bond pads of an IC are coupled by a connection including≥1 filled via for connecting to the top and/or bottom metal layer. A first metal pillar is between the first contact pad and first antenna, and a second metal pillar is between the second contact pad and second antenna. A first filled via is coupled to the first metal pillar providing a transmission line from the first contact pad to the first antenna. A second filled via is coupled to the first metal pillar providing a transmission line from the second contact pad to the second antenna.
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公开(公告)号:US11587891B2
公开(公告)日:2023-02-21
申请号:US17335010
申请日:2021-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yiqi Tang , Li Jiang , Rajen Manicon Murugan
IPC: H01L23/58 , H01L23/552 , H01L23/00
Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.
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公开(公告)号:US20220384353A1
公开(公告)日:2022-12-01
申请号:US17500086
申请日:2021-10-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Yiqi Tang , Rajen Manicon Murugan , Liang Wan , Makarand Ramkrishna Kulkarni , Jie Chen , Steven Alfred Kummerl
IPC: H01L23/538 , H01L23/00 , H01L21/48
Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.
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公开(公告)号:US20220376378A1
公开(公告)日:2022-11-24
申请号:US17736653
申请日:2022-05-04
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan
Abstract: An example semiconductor package comprises a patch antenna formed in a first conductor layer of a multilayer package substrate. The multilayer package substrate comprises conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers. The multilayer package substrate has a board side surface opposite a device side surface. The semiconductor package further comprises a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna. An antenna horn is mounted to the device side surface and aligned with the patch antenna using a mounting structure. The semiconductor package further comprises a reflector formed on a second conductor layer in the multilayer package substrate. The second conductor layer is positioned closer to the board side surface of the multilayer package substrate compared to the patch antenna.
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公开(公告)号:US20220359976A1
公开(公告)日:2022-11-10
申请号:US17566067
申请日:2021-12-30
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan , Juan Herbsommer
Abstract: In a described example, an apparatus includes: a patch antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna.
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公开(公告)号:US20220344796A1
公开(公告)日:2022-10-27
申请号:US17539110
申请日:2021-11-30
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan , Juan Alejandro Herbsommer
Abstract: A described example includes: an antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the antenna.
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公开(公告)号:US10475786B1
公开(公告)日:2019-11-12
申请号:US16037695
申请日:2018-07-17
Applicant: Texas Instruments Incorporated
Inventor: Yiqi Tang , Rajen Manicon Murugan , Makarand Ramkrishna Kulkarni
Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.
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