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    CIRCUITS AND METHODS TO CALIBRATE MIRROR DISPLACEMENT
    1.
    发明申请
    CIRCUITS AND METHODS TO CALIBRATE MIRROR DISPLACEMENT 有权

    公开(公告)号：US20220342202A1

    公开(公告)日：2022-10-27

    申请号：US17240483

    申请日：2021-04-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Robert Floyd Payne ,  James Norman Hall

    IPC: G02B26/08 ,  G01B7/06

    Abstract: A calibration circuit providing a programmable voltage generator that is selectively connectable to a first capacitor plate of a capacitive structure to supply a voltage thereto. A reference voltage generator is coupled to the output of the programmable voltage generator and generates a reference voltage. A comparator receives the reference voltage and a discharging voltage from the capacitive structure during a discharge period and, based on those inputs, generates a signal that is output to a digital controller. A constant current source is selectively connectable to the capacitive structure to generate a constant current. Based on the output of the comparator, the constant current, and a count representing a time during which the discharging voltage decreases, the digital controller measures capacitance to calibrate a movable mirror of the capacitive structure. During calibration, the digital controller controls the programmable voltage generator and a second capacitor plate of the capacitive structure.

    DIGITAL CLOCK-DUTY-CYCLE CORRECTION
    4.
    发明申请
    DIGITAL CLOCK-DUTY-CYCLE CORRECTION 审中-公开

    公开(公告)号：US20180309431A1

    公开(公告)日：2018-10-25

    申请号：US16023643

    申请日：2018-06-29

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mohammad Elbadry ,  Robert Floyd Payne ,  Gerd Schuppener

    IPC: H03K5/156 ,  H02M3/07

    CPC classification number: H03K5/1565 ,  H02M3/07

    Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.

    EMBEDDED CLOCK IN A COMMUNICATION SYSTEM
    5.
    发明申请
    EMBEDDED CLOCK IN A COMMUNICATION SYSTEM 有权

    公开(公告)号：US20170192449A1

    公开(公告)日：2017-07-06

    申请号：US14983776

    申请日：2015-12-30

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Floyd Payne

    IPC: G06F1/04 ,  H04B1/04 ,  H04B1/16

    CPC classification number: G06F1/04 ,  H04B1/04 ,  H04B1/16 ,  H04L25/4904

    Abstract: A method for transmitting a plurality of data bits and a clock signal on a return to zero (RZ) signal includes: transmitting a first voltage that is greater than a first threshold, the first voltage being decodable to first order of data bits; transmitting a second voltage that is between a second threshold and the first threshold, the second voltage being decodable to a second order of data bits; transmitting a third voltage that is between a third threshold and a fourth threshold, the third voltage being decodable to a third order of data bits; transmitting a fourth voltage that is greater in magnitude than the fourth threshold, the fourth voltage being decodable to a fourth order of data bits; and transitioning the clock signal in response to the RZ signal being between the second threshold and the third threshold.

    Method and system for comparing digital values
    7.
    发明授权
    Method and system for comparing digital values 有权
    比较数字值的方法和系统

    公开(公告)号：US08891717B1

    公开(公告)日：2014-11-18

    申请号：US13954424

    申请日：2013-07-30

    Applicant: Texas Instruments Incorporated

    Inventor： Robert Floyd Payne

    IPC: H03D3/24 ,  H04L7/00

    CPC classification number: H04L7/033 ,  H03L7/00

    Abstract: One bit is a smallest increment of binary measurement in first and second digital values. The first digital value is converted into a first analog signal. The second digital value is converted into a second analog signal. The first analog signal is augmented by a first amount that equates to less than the smallest increment of binary measurement, so that the augmented first analog signal by definition does not equal the second analog signal. The second analog signal is augmented by a second amount that equates to less than the smallest increment of binary measurement, so that the augmented second analog signal by definition does not equal the first analog signal. The augmented first analog signal is compared to the second analog signal, and a first signal is output in response thereto. The augmented second analog signal is compared to the first analog signal, and a second signal is output in response thereto. In response to the first and second signals, a determination is made about whether the first digital value is greater than the second digital value, whether the first digital value is less than the second digital value, and whether the first digital value is equal to the second digital value.

    Abstract translation: 一位是第一和第二数字值中二进制测量的最小增量。 第一数字值被转换成第一模拟信号。 第二数字值被转换成第二模拟信号。 第一模拟信号被增加等于小于二进制测量的最小增量的第一量，使得通过定义的增强的第一模拟信号不等于第二模拟信号。 第二模拟信号被增加等于小于二进制测量的最小增量的第二量，使得通过定义的增强的第二模拟信号不等于第一模拟信号。 将增大的第一模拟信号与第二模拟信号进行比较，并响应于此输出第一信号。 将增大的第二模拟信号与第一模拟信号进行比较，并响应于此输出第二信号。 响应于第一和第二信号，确定第一数字值是否大于第二数字值，第一数字值是否小于第二数字值，以及第一数字值是否等于第二数字值 第二数字值。

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