公开(公告)号：US20240006000A1

公开(公告)日：2024-01-04

申请号：US17854407

申请日：2022-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yunchen Qiu

IPC: G11C16/28 ,  H01L27/11517 ,  G11C16/30

CPC classification number: G11C16/28 ,  H01L27/11517 ,  G11C16/30 ,  G11C16/0433

Abstract: A nonvolatile memory (NVM) device having a programmable, self-tracking reference current design and a method of fabricating the same. A differential reference cell corresponding to a particular wordline is operable to generate a total reference cell current comprising an ON current and an OFF current driven by respective reference memory cells that form the differential reference cell. A reference current generator is operable to provide a scalable fraction of the total reference cell current as a reference current (IREF) for facilitating sensing operations by a sense amplifier block.

公开(公告)号：US09881687B2

公开(公告)日：2018-01-30

申请号：US15247352

申请日：2016-08-25

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/08 ,  G11C7/227 ,  G11C17/16

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

公开(公告)号：US11495301B2

公开(公告)日：2022-11-08

申请号：US17219092

申请日：2021-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yunchen Qiu ,  David Joseph Toops

IPC: G11C7/00 ,  G11C16/26

Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

公开(公告)号：US20180137928A1

公开(公告)日：2018-05-17

申请号：US15871381

申请日：2018-01-15

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/08 ,  G11C7/227 ,  G11C17/16

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

公开(公告)号：US20170047130A1

公开(公告)日：2017-02-16

申请号：US14824935

申请日：2015-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone ,  Yunchen Qiu ,  Sai Zhang

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C7/1006 ,  G11C7/24 ,  G11C16/22 ,  G11C16/349 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C2207/2263

Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

Abstract translation: 要写入存储器位置的数据字以多写避免（“MWA”）码字进行增量编码。 MWA码字不会将包含逻辑“0”的单位存储单元重新写入“0”状态，并且不将逻辑“1”重新写入已经写入逻辑“1”的单元。 “存储在查找表（”LUT“）中的潜在MWA代码字由差分字DELTA_D索引。 DELTA_D表示当前存储在存储器位置的数据字和要存储在存储器位置的新数据字（“NEW_D”）之间的按位差（“delta”）。 如果MWA代码字不违反多写回避原则，验证和选择逻辑将选择代表NEW_D的MWA代码字来写入。 一些实施例使用模式生成器生成MWA码字，而不是从LUT索引MWA码字。

公开(公告)号：US20210304824A1

公开(公告)日：2021-09-30

申请号：US17219092

申请日：2021-03-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Xiaowei Deng ,  Yunchen Qiu ,  David Joseph Toops

IPC: G11C16/26

Abstract: In one example a semiconductor device has a data latch that includes first and second transmission gates and first and second inverters. The first inverter is connected between a first terminal of the first transmission gate and a first terminal of the second transmission gate. The second inverter is connected between a second terminal of the first transmission gate and a second terminal of the second transmission gate. The data latch is configured to store a datum received at the connection between the first transmission gate and the second inverter, and to store a datum received at the connection between the second transmission gate and the first inverter.

公开(公告)号：US20170178742A1

公开(公告)日：2017-06-22

申请号：US15247352

申请日：2016-08-25

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/08 ,  G11C7/227 ,  G11C17/16

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

公开(公告)号：US10192629B2

公开(公告)日：2019-01-29

申请号：US15871381

申请日：2018-01-15

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16 ,  G11C7/08 ,  G11C7/22

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

公开(公告)号：US09715943B2

公开(公告)日：2017-07-25

申请号：US14824935

申请日：2015-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone ,  Yunchen Qiu ,  Sai Zhang

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/36 ,  G11C16/34 ,  G11C7/10

CPC classification number: G11C29/38 ,  G11C7/1006 ,  G11C7/24 ,  G11C16/22 ,  G11C16/349 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C2207/2263

Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.