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    SEMICONDUCTOR MEMORY CELL MULTI-WRITE AVOIDANCE ENCODING APPARATUS, SYSTEMS AND METHODS
    1.
    发明申请
    SEMICONDUCTOR MEMORY CELL MULTI-WRITE AVOIDANCE ENCODING APPARATUS, SYSTEMS AND METHODS 有权
    半导体存储器单元多写避免编码设备，系统和方法

    公开(公告)号：US20170047130A1

    公开(公告)日：2017-02-16

    申请号：US14824935

    申请日：2015-08-12

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Yuming Zhu ,  Manish Goel ,  Clive Bittlestone ,  Yunchen Qiu ,  Sai Zhang

    IPC: G11C29/38 ,  G11C29/36

    CPC classification number: G11C29/38 ,  G11C7/1006 ,  G11C7/24 ,  G11C16/22 ,  G11C16/349 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C2207/2263

    Abstract: Data words to be written to a memory location are delta encoded in multi-write avoidance (“MWA”) code words. MWA code words result in no re-writing of single-bit storage cells containing logical “0's” to a “0” state and no re-writing of logical “1's” to cells that have already been written once to a logical “1.” Potential MWA code words stored in a look-up table (“LUT”) are indexed by a difference word DELTA_D. DELTA_D represents a bitwise difference (“delta”) between a data word currently stored at the memory location and a new data word (“NEW_D”) to be stored at the memory location. Validation and selection logic chooses an MWA code word representing NEW_D to be written if the MWA code word does not violate the principle of multi-write avoidance. Some embodiments generate the MWA code words using a pattern generator rather than indexing the MWA code words from a LUT.

    Abstract translation: 要写入存储器位置的数据字以多写避免（“MWA”）码字进行增量编码。 MWA码字不会将包含逻辑“0”的单位存储单元重新写入“0”状态，并且不将逻辑“1”重新写入已经写入逻辑“1”的单元。 “存储在查找表（”LUT“）中的潜在MWA代码字由差分字DELTA_D索引。 DELTA_D表示当前存储在存储器位置的数据字和要存储在存储器位置的新数据字（“NEW_D”）之间的按位差（“delta”）。 如果MWA代码字不违反多写回避原则，验证和选择逻辑将选择代表NEW_D的MWA代码字来写入。 一些实施例使用模式生成器生成MWA码字，而不是从LUT索引MWA码字。

    Error correction code management of write-once memory codes
    3.
    发明授权
    Error correction code management of write-once memory codes 有权

    公开(公告)号：US10191801B2

    公开(公告)日：2019-01-29

    申请号：US15678315

    申请日：2017-08-16

    Applicant: Texas Instruments Incorporated

    Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

    IPC: G06F11/08 ,  G11C29/52 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02 ,  H03M13/13

    Abstract: Disclosed embodiments include an electronic device having a write-once memory (WOM) and a memory controller. The memory controller includes a host interface receiving a data word including first and second symbols, each having at least two bits, a WOM controller that encodes the first and second symbols and outputs a WOM-encoded word including first and second WOM codes corresponding to the first and second symbols, respectively, an error correction code (ECC) controller that encodes the WOM-encoded word and outputs an ECC-encoded word including the first and second WOM codes and a first set of ECC bits corresponding to a first write operation, and a memory device interface that writes the ECC-encoded word the WOM device in the first write operation. Each of the first and second WOM codes include at least three bits with at least two of the at least three bits having the same logic value.

    DUAL-MODE ERROR-CORRECTION CODE/WRITE-ONCE MEMORY CODEC
    8.
    发明申请
    DUAL-MODE ERROR-CORRECTION CODE/WRITE-ONCE MEMORY CODEC 有权
    双模式错误修正代码/写入存储器编解码器

    公开(公告)号：US20160342471A1

    公开(公告)日：2016-11-24

    申请号：US14720442

    申请日：2015-05-22

    Applicant: Texas Instruments Incorporated

    Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/159 ,  H03M13/19 ,  H03M13/353 ,  H03M13/616

    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

    Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如用于在WOM（只写存储器）模式和ECC（纠错码）模式之一中进行选择的控制器。 编解码器被布置为在选择的模式下操作。 以ECC模式操作的编解码器被配置为响应于第一接收数据字的ECC奇偶校验位来识别至少一个位错误的位位置。 在WOM模式下操作的编解码器被布置成从WOM设备中的寻址位置接收WOM编码的字，以接收待编码和写入到寻址位置的第二接收数据字，并且生成WOM编码字 用于写入WOM设备中的寻址位置。 用于写入寻址位置的WOM编码字可选地被ECC编码。

    ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES
    9.
    发明申请
    ERROR CORRECTION CODE MANAGEMENT OF WRITE-ONCE MEMORY CODES 有权
    一般存储器代码的错误修正代码管理

    公开(公告)号：US20160328289A1

    公开(公告)日：2016-11-10

    申请号：US14703714

    申请日：2015-05-04

    Applicant: Texas Instruments Incorporated

    Inventor： Sai Zhang ,  Yuming Zhu ,  Clive Bittlestone ,  Srinath Ramaswamy

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/08 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1072 ,  G06F11/1076 ,  G06F12/0246 ,  G11C29/52 ,  H03M13/13

    Abstract: A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a host processor is arranged to send a data word that is to be stored in a WOM (Write-Only Memory) device. A host interface is arranged to receive the first data word for processing by a WOM controller and an ECC controller. The WOM controller is for generating a first WOM-encoded word in response to an original symbol of the first data word, while the ECC controller is for generating a first set of ECC bits in response to the original symbol of the first data word. A memory device interface is for writing the first WOM-encoded word and the first set of ECC bits to the WOM device in accordance with the memory address associated with the first data word.

    Abstract translation: 一次写入存储器（WOM）代码的纠错码（ECC）管理系统包括例如主机处理器被配置为发送要存储在WOM（只写存储器）设备中的数据字。 主机接口被布置为接收第一数据字以供WOM控制器和ECC控制器处理。 WOM控制器用于响应于第一数据字的原始符号来生成第一WOM编码字，而ECC控制器用于响应于第一数据字的原始符号来生成第一组ECC位。 存储器件接口用于根据与第一数据字相关联的存储器地址将第一WOM编码字和第一组ECC位写入WOM器件。

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