公开(公告)号：US20220165871A1

公开(公告)日：2022-05-26

申请号：US17324893

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/68 ,  H01L21/02 ,  H01L29/24 ,  H01L29/76 ,  H01L29/786 ,  H01L29/66

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US12027628B2

公开(公告)日：2024-07-02

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/68 ,  H01L29/76

CPC classification number: H01L29/78645 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US20210226059A1

公开(公告)日：2021-07-22

申请号：US17221988

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Chiao-Tung University

Inventor： Chao-Hsin Chien ,  Yu-Che Chou ,  Chien-Wei Tsai ,  Chin-Ya Yi

IPC: H01L29/78 ,  H01L29/792 ,  H01L21/225 ,  H01L29/66

Abstract: Structures and methods of forming self-aligned unsymmetric gate (SAUG) FinFET are provided. The SAUG FinFET structure has two different gate structures on opposite sides of each fin: a programming gate structure and a switching gate structure. The SAUG FinFET may be used as non-volatile memory (NVM) storage element that may be electrically programmed by trapping charges in the charge trapping dielectric (e.g., Si3N4) with appropriate bias on the control gate of the programming gate structure. The stored data may be sensed by sensing the channel current through the SAUG FinFET in response to a bias on the switching gate of the switching gate structure.

公开(公告)号：US09859276B2

公开(公告)日：2018-01-02

申请号：US15292406

申请日：2016-10-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO-TUNG UNIVERSITY

Inventor： Chao-Hsin Chien ,  Chen-Han Chou ,  Cheng-Ting Chung ,  Samuel C. Pan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L27/0207 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/7853

Abstract: A semiconductor device including at least one fin disposed on a surface of a semiconductor substrate is provided. The fin includes a main portion extending along a first direction, and at least one secondary portion extending outward from the main portion along a second direction not collinear with the first direction.

公开(公告)号：US09837538B2

公开(公告)日：2017-12-05

申请号：US15214777

申请日：2016-07-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO TUNG UNIVERSITY

Inventor： Chao-Hsin Chien ,  Chi-Wen Liu ,  Chen-Han Chou

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.

公开(公告)号：US20230253503A1

公开(公告)日：2023-08-10

申请号：US18303924

申请日：2023-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L29/68 ,  H01L21/02 ,  H01L29/66 ,  H01L29/76 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/78645 ,  H01L29/685 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/66969 ,  H01L29/7606 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/24 ,  H01L29/42384

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US11670720B2

公开(公告)日：2023-06-06

申请号：US17324893

申请日：2021-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yan Chung ,  Chao-Ching Cheng ,  Chao-Hsin Chien

IPC: H01L29/786 ,  H01L29/68 ,  H01L21/02 ,  H01L29/66 ,  H01L29/76 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/78645 ,  H01L21/0262 ,  H01L21/02565 ,  H01L21/02568 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/685 ,  H01L29/7606 ,  H01L29/7869 ,  H01L29/78648 ,  H01L29/78696

Abstract: In an embodiment, a method includes forming a first gate electrode over a substrate. The method also includes forming a first gate dielectric layer over the first gate electrode. The method also includes depositing a semiconductor layer over the first gate dielectric layer. The method also includes forming source/drain regions over the first gate dielectric layer and the semiconductor layer, the source/drain regions overlapping ends of the semiconductor layer. The method also includes forming a second gate dielectric layer over the semiconductor layer and the source/drain regions. The method also includes and forming a second gate electrode over the second gate dielectric layer.

公开(公告)号：US10453688B2

公开(公告)日：2019-10-22

申请号：US15253074

申请日：2016-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO TUNG UNIVERSITY

Inventor： Chao-Hsin Chien ,  Chi-Wen Liu ,  Chung-Chun Hsu ,  Wei-Chun Chi

IPC: H01L21/24 ,  H01L21/285 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L29/45 ,  H01L29/16

Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.

公开(公告)号：US10269966B2

公开(公告)日：2019-04-23

申请号：US15807317

申请日：2017-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL CHIAO TUNG UNIVERSITY

Inventor： Chao-Hsin Chien ,  Chi-Wen Liu ,  Chen-Han Chou

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.