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    VOLTAGE SUPPLY SELECTION CIRCUIT
    1.
    发明申请
    VOLTAGE SUPPLY SELECTION CIRCUIT 有权

    公开(公告)号：US20230054498A1

    公开(公告)日：2023-02-23

    申请号：US17406273

    申请日：2021-08-19

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chia-Chen KUO ,  Yangsyu LIN ,  Yu-Hao HSU ,  Cheng Hung LEE ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG

    IPC: H03K3/012

    Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.

    I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS
    3.
    发明申请
    I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS 有权

    公开(公告)号：US20210226806A1

    公开(公告)日：2021-07-22

    申请号：US17222806

    申请日：2021-04-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Che TSAI ,  Shih-Lien Linus LU ,  Cheng Hung LEE ,  Chia-En HUANG

    IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

    Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE
    4.
    发明申请
    LEAKAGE PATHWAY PREVENTION IN A MEMORY STORAGE DEVICE 审中-公开

    公开(公告)号：US20200005835A1

    公开(公告)日：2020-01-02

    申请号：US16263904

    申请日：2019-01-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shang-Chi WU ,  Cheng Hung LEE ,  Chien-Kuo SU ,  Chiting CHENG ,  Yu-Hao HSU ,  Yangsyu LIN

    IPC: G11C7/10 ,  G11C7/12

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices. This specialized circuitry, also referred to as a write driver, writes the electronic data onto these data lines for storage in the one or more memory cells during the write mode of operation.

    I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS
    5.
    发明公开
    I/O CIRCUIT DESIGN FOR SRAM-BASED PUF GENERATORS 审中-公开

    公开(公告)号：US20240214226A1

    公开(公告)日：2024-06-27

    申请号：US18602593

    申请日：2024-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Che TSAI ,  Shih-Lien Linus LU ,  Cheng Hung LEE ,  Chia-En HUANG

    IPC: H04L9/32 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/08

    CPC classification number: H04L9/3278 ,  G11C7/06 ,  G11C11/4091 ,  H04L9/0861

    Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.

    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT
    6.
    发明申请
    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT 审中-公开
    用于读取辅助以补偿弱位的方法和装置

    公开(公告)号：US20150131394A1

    公开(公告)日：2015-05-14

    申请号：US14603393

    申请日：2015-01-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

    Abstract translation: 记忆辅助装置包括检测电路和补偿电路。 检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。 如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

    STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT
    7.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT 有权

    公开(公告)号：US20220085035A1

    公开(公告)日：2022-03-17

    申请号：US17125688

    申请日：2020-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Sheng WANG ,  Yangsyu LIN ,  Cheng Hung LEE

    IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

    Abstract: The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.

    Balanced Coupling Structure for Physically Unclonable Function (PUF) Application
    10.
    发明申请
    Balanced Coupling Structure for Physically Unclonable Function (PUF) Application 审中-公开

    公开(公告)号：US20200020364A1

    公开(公告)日：2020-01-16

    申请号：US16160397

    申请日：2018-10-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jui-Che TSAI ,  Cheng Hung LEE ,  Shih-Lien Linus LU ,  Yi-Ju CHEN

    IPC: G11C7/08 ,  G11C7/12 ,  H04L9/32

    Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

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