公开(公告)号：US20220208986A1

公开(公告)日：2022-06-30

申请号：US17654807

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. MORE

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US20160225906A1

公开(公告)日：2016-08-04

申请号：US14613663

申请日：2015-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsan-Chun WANG ,  Ziwei FANG ,  Chien-Tai CHAN ,  Da-Wen LIN ,  Huicheng CHANG

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括在衬底的上部具有掺杂区的衬底。 掺杂区域掺杂有第一导电类型的第一掺杂剂。 半导体器件结构包括在衬底上的一个鳍结构。 通过鳍结构暴露的掺杂区域的第一掺杂剂浓度大于由鳍结构覆盖的掺杂区域的第二掺杂剂浓度。 半导体器件结构包括在衬底上并在鳍结构的两个相对侧的隔离层。 半导体器件结构包括隔离层上的栅极和鳍结构。

公开(公告)号：US20240371970A1

公开(公告)日：2024-11-07

申请号：US18772213

申请日：2024-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. MORE

IPC: H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US20200058747A1

公开(公告)日：2020-02-20

申请号：US16432594

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting FANG ,  Da-Wen LIN ,  Fu-Kai YANG ,  Chen-Ming LEE ,  Mei-Yun WANG

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

公开(公告)号：US20250022931A1

公开(公告)日：2025-01-16

申请号：US18779444

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Da-Wen LIN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20220238678A1

公开(公告)日：2022-07-28

申请号：US17465300

申请日：2021-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin LEE ,  Choh Fei YEAP ,  Da-Wen LIN ,  Chih Yeh

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/66

Abstract: Methods include providing a first fin structure and a second fin structure each extending from a substrate. A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

公开(公告)号：US20200066869A1

公开(公告)日：2020-02-27

申请号：US16673661

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Cheng-Yi PENG ,  Yin-Pin WANG ,  Kuo-Feng YU ,  Da-Wen LIN ,  Jian-Hao CHEN ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.