公开(公告)号：US20160204255A1

公开(公告)日：2016-07-14

申请号：US15076762

申请日：2016-03-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/161 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

公开(公告)号：US20250022931A1

公开(公告)日：2025-01-16

申请号：US18779444

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Da-Wen LIN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.

公开(公告)号：US20190181048A1

公开(公告)日：2019-06-13

申请号：US16271522

申请日：2019-02-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L21/8234 ,  H01L29/161 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

公开(公告)号：US20240079483A1

公开(公告)日：2024-03-07

申请号：US18124980

申请日：2023-03-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hung LIN ,  I-Hsieh WONG ,  Tzu-Hua CHIU ,  Cheng-Yi PENG ,  Chia-Pin LIN

IPC: H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/775 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a fin base disposed on the substrate, nanostructured channel regions disposed on a first portion of the fin base, a gate structure surrounding the nanostructured channel regions, a source/drain (S/D) region disposed on a second portion of the fin base, and an isolation structure disposed between the S/D region and the second portion of the fin base. The isolation structure includes an undoped semiconductor layer disposed on the second portion of the fin base, a silicon-rich dielectric layer disposed on the undoped semiconductor layer, and an air spacer disposed on the silicon-rich dielectric layer.

公开(公告)号：US20130109152A1

公开(公告)日：2013-05-02

申请号：US13719460

申请日：2012-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang HUANG ,  Chia-Pin LIN

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

Abstract: An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Abstract translation: 集成电路器件包括在半导体衬底上延伸并在第一纵向方向上延伸的栅极区域。 第一翅片具有第一侧壁，其在半导体衬底上方的第二纵向方向上延伸，使得第一鳍片与栅极区域相交。 第二鳍片具有在半导体衬底上方的第二方向上延伸的第二侧壁，使得第二鳍片与栅极区域相交。 在第一和第二鳍片的第一和第二侧壁之间的半导体衬底中形成浅沟槽隔离（STI）区域。 布置在所述第一绝缘层之上和所述第一和第二鳍片的顶表面之上的导电层。 第一绝缘层设置在STI区的上表面和导电层的下表面之间，以将STI区与导电层分离。

公开(公告)号：US20220336612A1

公开(公告)日：2022-10-20

申请号：US17548179

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hung CHANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG ,  Chia-Pin LIN ,  Wei-Yang LEE ,  Yen-Sheng LU

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

公开(公告)号：US20150115322A1

公开(公告)日：2015-04-30

申请号：US14554179

申请日：2014-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Kai CHEN ,  Hsien-Hsin LIN ,  Chia-Pin LIN ,  Chien-Tai CHAN ,  Yuan-Ching PENG

IPC: H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

Abstract: A method includes forming a first fin and a second fin extending above a semiconductor substrate, with a shallow trench isolation (STI) region between them. A space is defined between the first and second fins above a top surface of the STI region. A first height is defined between the top surface of the STI region and top surfaces of the first and second fins. A flowable dielectric material is deposited into the space. The dielectric material has a top surface above the top surface of the STI region, so as to define a second height between the top surface of the dielectric material and the top surfaces of the first and second fins. The second height is less than the first height. First and second fin extensions are epitaxially formed above the dielectric, on the first and second fins, respectively, after the depositing step.

Abstract translation: 一种方法包括形成在半导体衬底之上延伸的第一鳍片和第二鳍片，在它们之间具有浅沟槽隔离（STI）区域。 在STI区域的顶表面之上的第一和第二鳍之间限定空间。 第一高度限定在STI区域的顶表面和第一鳍片和第二鳍片的顶表面之间。 可流动的电介质材料沉积到该空间中。 电介质材料具有在STI区域的顶表面上方的顶表面，以便在介电材料的顶表面和第一和第二鳍片的顶表面之间限定第二高度。 第二个高度小于第一个高度。 在沉积步骤之后，第一和第二鳍片延伸部分别外延形成在电介质上方，分别在第一和第二鳍片上。