公开(公告)号：US20200043924A1

公开(公告)日：2020-02-06

申请号：US16596209

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han CHEN ,  Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG ,  Jr-Hung LI ,  Bo-Cyuan LU

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure, and a first capping layer formed over the first gate structure. The FinFET device structure includes a first etching stop layer formed over the first capping layer and the first gate structure, and a top surface and a sidewall surface of the first capping layer are in direct contact with the first etching stop layer.

公开(公告)号：US20180190504A1

公开(公告)日：2018-07-05

申请号：US15649909

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC: H01L21/311 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L21/31116 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76837 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, an interlayer dielectric (ILD) layer is formed over an underlying structure. The underlying structure includes gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate, source/drain epitaxial layers disposed between two adjacent gate structures, and an etching-stop layer (ESL) covering the source/drain epitaxial layers. An opening is formed in the ILD layer by etching. A dielectric filling layer is formed in the opening. By using wet etching, the ILD layer disposed above the source/drain epitaxial layers is removed. The ESL disposed on the source/drain epitaxial layers is removed, thereby at least partially exposing the source/drain epitaxial layers. A conductive material is formed over the exposed source/drain epitaxial layers.

公开(公告)号：US20170317205A1

公开(公告)日：2017-11-02

申请号：US15590210

申请日：2017-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming LEE ,  Liang-Yi CHEN ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L21/02057 ,  H01L21/02532 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for manufacturing a semiconductor device is provided, including forming a plurality of fins on a semiconductor substrate, and forming source/drain regions on the fins. The source/drain regions have an uneven surface with a mean surface roughness, Ra, of about 10 nm to about 50 nm. A smoothing layer is formed on the source/drain regions filling the uneven surface. An etch stop layer is formed overlying the smoothing layer. A portion of the etch stop layer is removed to expose a portion of the smoothing layer. The exposed smoothing layer is removed, and a contact layer is formed on the source/drain regions.

公开(公告)号：US20190013208A1

公开(公告)日：2019-01-10

申请号：US16129741

申请日：2018-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768

Abstract: A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

公开(公告)号：US20200243344A1

公开(公告)日：2020-07-30

申请号：US16774823

申请日：2020-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC: H01L21/311 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/088

Abstract: A semiconductor device includes: an isolation insulating layer; fin structures protruding from the isolation insulating layer; gate structures, each having a metal gate and a cap insulating layer disposed over the metal gate; a first source/drain epitaxial layer and a second source/drain epitaxial layer disposed between two adjacent gate structures; and a first conductive contact disposed on the first source/drain epitaxial layer, and a second conductive contact disposed on the second source/drain epitaxial layer; a separation isolation region disposed between the first and second conductive contact; and an insulating layer disposed between the separation isolation region and the isolation insulating layer. The separation isolation region is made of a different material than the insulating layer.

公开(公告)号：US20200058747A1

公开(公告)日：2020-02-20

申请号：US16432594

申请日：2019-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting FANG ,  Da-Wen LIN ,  Fu-Kai YANG ,  Chen-Ming LEE ,  Mei-Yun WANG

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

Abstract: A FinFET device structure and method for forming the same is provided. The FinFET device structure includes an isolation structure formed over a substrate, and a gate structure formed over the isolation structure. The FinFET device structure includes a first dielectric layer formed over the isolation structure and adjacent to the gate structure and a source/drain (S/D) contact structure formed in the first dielectric layer. The FinFET device structure also includes a deep contact structure formed through the first dielectric layer and adjacent to the S/D contact structure. The deep contact structure is through the isolation structure, and a bottom surface of the S/D contact structure is higher than a bottom surface of the deep contact structure.

公开(公告)号：US20190148225A1

公开(公告)日：2019-05-16

申请号：US16124527

申请日：2018-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yuan CHEN ,  Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L23/522 ,  H01L29/78

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a gate structure over a fin structure. The method also includes forming an S/D contact structure over a S/D structure and depositing a protection layer over the S/D contact structure. The portion layer and the S/D contact structure are made of different materials. The method further includes forming an etching stop layer over the protection layer and forming a dielectric layer over the etching stop layer. The method includes forming a first recess through the dielectric layer and the etching stop layer to expose the protection layer and forming an S/D conductive plug in the first recess. The S/D conductive plug includes a barrier layer directly on the protection layer, and the protection layer and the barrier layer are made of different materials.

公开(公告)号：US20170207135A1

公开(公告)日：2017-07-20

申请号：US15479418

申请日：2017-04-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG ,  Kuo-Yi CHAO

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L21/823864 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.

公开(公告)号：US20190164960A1

公开(公告)日：2019-05-30

申请号：US15821970

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han CHEN ,  Chen-Ming LEE ,  Fu-Kai YANG ,  Mei-Yun WANG ,  Jr-Hung LI ,  Bo-Cyuan LU

IPC: H01L27/088 ,  H01L29/423 ,  H01L21/8234

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and a first gate structure formed over the fin structure. The FinFET device structure also includes a first capping layer formed over the first gate structure and a first etching stop layer over the first capping layer and the first gate structure. The FinFET device structure further includes a first source/drain (S/D) contact structure formed over the fin structure and adjacent to the first gate structure. A portion of the first etching stop layer which is directly above the first capping layer is higher than another portion of the first etching stop layer which is directly above the first gate spacer layer.