公开(公告)号：US20200027793A1

公开(公告)日：2020-01-23

申请号：US16585859

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20180102292A1

公开(公告)日：2018-04-12

申请号：US15830859

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20160163820A1

公开(公告)日：2016-06-09

申请号：US15016214

申请日：2016-02-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN

IPC: H01L29/66 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L29/6681 ,  H01L21/2855 ,  H01L21/28556 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure over a substrate. Next, a dummy gate is deposited across over the fin structure. The method continues with forming a pair of first spacers on sidewalls of the dummy gate. Then, a source/drain region is formed in the fin structure not covered by the dummy gate. The method further includes removing the dummy gate to expose the fin structure. After that, the first spacers are truncated, and a gate stack is formed to cover the exposed fin structure and top surfaces of the first spacers.

Abstract translation: 提供一种制造FinFET和FinFET的方法。 在各种实施例中，制造FinFET的方法包括在衬底上形成翅片结构。 接下来，跨越翅片结构沉积虚拟栅极。 该方法继续在伪栅极的侧壁上形成一对第一间隔物。 然后，在未被虚拟栅极覆盖的鳍结构中形成源极/漏极区域。 该方法还包括去除伪栅极以暴露翅片结构。 之后，第一间隔件被截断，并且形成一个栅叠层以覆盖暴露的散热片结构和第一间隔件的顶表面。

公开(公告)号：US20230369490A1

公开(公告)日：2023-11-16

申请号：US18346480

申请日：2023-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/0847

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

公开(公告)号：US20160149040A1

公开(公告)日：2016-05-26

申请号：US14819602

申请日：2015-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chia-Ling CHAN ,  Chien-Tai CHAN

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/785

Abstract: A FinFET includes a fin structure, a gate and a source-drain region. The fin structure is over a substrate and has a recess of an upper surface of the fin structure and a doped region in the fin structure and adjacent to the recess. The gate protrudes from the recess and across over the fin structure. The source-drain region is in the fin structure and adjacent to the doped region. Methods for forming the FinFET are also provided.

Abstract translation: FinFET包括鳍结构，栅极和源极 - 漏极区域。 翅片结构在衬底之上，并且具有翅片结构的上表面的凹部和鳍结构中的与凹部相邻的掺杂区域。 门从凹槽突出并跨过翅片结构。 源极 - 漏极区域处于鳍状结构并且与掺杂区域相邻。 还提供了形成FinFET的方法。

公开(公告)号：US20210273101A1

公开(公告)日：2021-09-02

申请号：US17320687

申请日：2021-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Ting-Yeh CHEN ,  Chii-Horng LI ,  Feng-Cheng YANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

Abstract: A method includes forming a fin in a substrate. The fin is etched to create a source/drain recess. A source/drain feature is formed in the source/drain recess, in which a lattice constant of the source/drain feature is greater than a lattice constant of the fin. An epitaxy coat is grown over the source/drain feature, in which a lattice constant of the epitaxy coat is smaller than a lattice constant of the fin.

公开(公告)号：US20180138172A1

公开(公告)日：2018-05-17

申请号：US15353933

申请日：2016-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Han-Wei WU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/41791

Abstract: A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

公开(公告)号：US20170256456A1

公开(公告)日：2017-09-07

申请号：US15061609

申请日：2016-03-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang LEE ,  Feng-Cheng YANG ,  Ting-Yeh CHEN

IPC: H01L21/8234 ,  H01L29/08 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/823425 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20250022931A1

公开(公告)日：2025-01-16

申请号：US18779444

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Yeh CHEN ,  Wei-Yang LEE ,  Chia-Pin LIN ,  Da-Wen LIN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: Gate spacer that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a gate stack disposed over a semiconductor layer and a gate spacer disposed on a sidewall of the gate stack. A source/drain feature is disposed in the semiconductor layer and adjacent the gate spacer. A low-k contact etch stop layer is disposed on a top surface and a sidewall of the gate spacer and a portion of the gate spacer is disposed between the low-k contact etch stop layer and the semiconductor layer. A source/drain contact is disposed on the source/drain feature and adjacent the low-k contact etch stop layer.