公开(公告)号：US20240379434A1

公开(公告)日：2024-11-14

申请号：US18780838

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

公开(公告)号：US12136567B2

公开(公告)日：2024-11-05

申请号：US17838723

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

公开(公告)号：US20220352019A1

公开(公告)日：2022-11-03

申请号：US17859981

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Ming-Han Lee ,  Shin-Yi Yang ,  Yung-Hsu Wu ,  Chia-Tien Wu ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a second contact feature over the first contact feature, a barrier layer between the second dielectric layer and the second contact feature, and a liner between the barrier layer and the second contact feature. An interface between the first contact feature and the second contact feature includes the liner but is free of the barrier layer.

公开(公告)号：US20220328351A1

公开(公告)日：2022-10-13

申请号：US17838723

申请日：2022-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

公开(公告)号：US11201106B2

公开(公告)日：2021-12-14

申请号：US16752158

申请日：2020-01-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Ming-Han Lee ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L23/522 ,  H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/00 ,  H01L23/535 ,  H01L23/482

Abstract: A structure includes a first substrate having a front side and a back side and a second substrate having a front side and a back side, wherein the back side of the second substrate is attached to the back side of the first substrate. The structure further includes a device layer over the front side of the second substrate; a first conductor going through a semiconductor layer in the second substrate; and a conductive connection that connects the first conductor to a conductive feature in the device layer.

公开(公告)号：US20210384074A1

公开(公告)日：2021-12-09

申请号：US16895338

申请日：2020-06-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping Chen ,  Shau-Lin Shue ,  Min Cao

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a semiconductor substrate and forming a patterned metal structure on the semiconductor substrate, wherein the patterned metal structure includes a first metal layer and a second metal layer deposited in a single deposition step. The method further includes etching a portion of the second metal layer thereby forming a metal plug in the second metal layer, the first metal layer of the patterned metal structure having a first metal feature underlying and contacting the metal plug.

公开(公告)号：US20200111702A1

公开(公告)日：2020-04-09

申请号：US16704195

申请日：2019-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ethan Hsiao ,  Chien Wen Lai ,  Chih-Ming Lai ,  Yi-Hsiung Lin ,  Cheng-Chi Chuang ,  Hsin-Ping Chen ,  Ru-Gun Liu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/8234

Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.

公开(公告)号：US12094946B2

公开(公告)日：2024-09-17

申请号：US17718080

申请日：2022-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chih Wang ,  Yu-Chieh Liao ,  Tai-I Yang ,  Hsin-Ping Chen

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7827 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/7869 ,  H01L29/78696

Abstract: A device includes a nanostructure, a gate dielectric layer, a gate electrode, and a gate contact. The nanostructure is over a substrate. The gate dielectric layer laterally surrounds the nanostructure. The gate electrode laterally surrounds the gate dielectric layer. The gate electrode has a bottom surface and a top surface both higher than a bottom end of the nanostructure. The gate electrode has a horizontal dimension decreasing from the bottom surface to the top surface. The gate contact is electrically coupled to the gate electrode.

公开(公告)号：US12062611B2

公开(公告)日：2024-08-13

申请号：US17665703

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Li-Lin Su ,  Yung-Hsu Wu ,  Hsin-Ping Chen ,  Cheng-Chi Chuang

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76898 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/5226

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.

公开(公告)号：US11302792B2

公开(公告)日：2022-04-12

申请号：US17006802

申请日：2020-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chih Wang ,  Yu-Chieh Liao ,  Tai-I Yang ,  Hsin-Ping Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786

Abstract: A device includes a nanowire, a gate dielectric layer, a gate electrode, a gate pickup metal layer, and a gate contact. The nanowire extends in a direction perpendicular to a top surface of a substrate. The gate dielectric layer laterally surrounds the nanowire. The gate electrode laterally surrounds the gate dielectric layer. The gate pickup metal layer is in contact with a bottom surface of the gate electrode and extends laterally past opposite sidewalls of the gate electrode. The gate contact is in contact with the gate pickup metal layer.