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公开(公告)号:US20240339406A1
公开(公告)日:2024-10-10
申请号:US18749812
申请日:2024-06-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Li-Lin Su , Yung-Hsu Wu , Hsin-Ping Chen , Cheng-Chi Chuang
IPC: H01L23/528 , H01L21/768 , H01L21/8234 , H01L23/522
CPC classification number: H01L23/5283 , H01L21/7682 , H01L21/76832 , H01L21/76834 , H01L21/76898 , H01L21/823431 , H01L21/823475 , H01L21/823481 , H01L23/5226
Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
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公开(公告)号:US20220350262A1
公开(公告)日:2022-11-03
申请号:US17868398
申请日:2022-07-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I YANG , Wei-Chen Chu , Hsiang-Wei Liu , Shau-Lin Shue , Li-Lin Su , Yung-Hsu Wu
IPC: G03F7/20 , H01L21/768 , G03F7/004 , G03F7/00 , G03F7/09
Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
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公开(公告)号:US11422475B2
公开(公告)日:2022-08-23
申请号:US16722621
申请日:2019-12-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Wei-Chen Chu , Hsiang-Wei Liu , Shau-Lin Shue , Li-Lin Su , Yung-Hsu Wu
IPC: G03F7/20 , H01L21/768 , G03F7/004 , G03F7/00 , G03F7/09
Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
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公开(公告)号:US11127680B2
公开(公告)日:2021-09-21
申请号:US15632184
申请日:2017-06-23
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Shih-Kang Fu , Hsien-Chang Wu , Li-Lin Su , Ming-Han Lee , Shau-Lin Shue
IPC: H01L23/535 , H01L23/532 , H01L21/768 , H01L21/321 , H01L21/3213 , H01L23/522 , H01L23/528
Abstract: In a method for manufacturing a semiconductor device, a dielectric layer is formed over a substrate. A first pattern and a second pattern are formed in the first interlayer dielectric layer. The first pattern has a width greater than a width of the second pattern. A first metal layer is formed in the first pattern and the second pattern. A second metal layer is formed in the first pattern. A planarization operation is performed on the first and second metal layers so that a first metal wiring by the first pattern and a second metal wiring by the second pattern are formed. A metal material of the first metal layer is different from a metal material of the second metal layer. The first metal wiring includes the first and second metal layers and the second metal wiring includes the first metal layer but does not include the second metal layer.
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公开(公告)号:US20240085803A1
公开(公告)日:2024-03-14
申请号:US18514254
申请日:2023-11-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Wei-Chen Chu , Hsiang-Wei Liu , Shau-Lin Shue , Li-Lin Su , Yung-Hsu Wu
IPC: G03F7/00 , G03F7/004 , G03F7/09 , H01L21/768
CPC classification number: G03F7/70633 , G03F7/0035 , G03F7/0043 , G03F7/0047 , G03F7/094 , G03F7/70625 , H01L21/76807 , H01L21/7682 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L21/76849
Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
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公开(公告)号:US20220157720A1
公开(公告)日:2022-05-19
申请号:US17665703
申请日:2022-02-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Li-Lin Su , Yung-Hsu Wu , Hsin-Ping Chen , Cheng-Chi Chuang
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L21/8234
Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
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公开(公告)号:US11251131B2
公开(公告)日:2022-02-15
申请号:US16904026
申请日:2020-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Li-Lin Su , Ching-Hua Hsieh , Huang-Ming Chen , Hsueh Wen Tsau
IPC: H01L23/535 , H01L29/49 , H01L23/532 , H01L23/485 , H01L23/522 , H01L29/66 , H01L21/768 , H01L21/28
Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
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公开(公告)号:US11244898B2
公开(公告)日:2022-02-08
申请号:US16380386
申请日:2019-04-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Li-Lin Su , Yung-Hsu Wu , Hsin-Ping Chen , Cheng-Chi Chuang
IPC: H01L23/528 , H01L21/768 , H01L23/522 , H01L21/8234
Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece having an interconnect structure that includes a first conductive feature, a second conductive feature disposed beside the first conductive feature, and an inter-level dielectric disposed between the first conductive feature and the second conductive feature. A conductive material of an etch stop layer is selectively deposited on the first conductive feature and on the second conductive feature without depositing the conductive material on the inter-level dielectric, and the inter-level dielectric is removed to form a gap between the first conductive feature and the second conductive feature.
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公开(公告)号:US11860550B2
公开(公告)日:2024-01-02
申请号:US17868398
申请日:2022-07-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Wei-Chen Chu , Hsiang-Wei Liu , Shau-Lin Shue , Li-Lin Su , Yung-Hsu Wu
IPC: G03F7/00 , H01L21/768 , G03F7/004 , G03F7/09
CPC classification number: G03F7/70633 , G03F7/0035 , G03F7/0043 , G03F7/0047 , G03F7/094 , G03F7/70625 , H01L21/7682 , H01L21/76807 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L21/76849
Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.
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公开(公告)号:US11088020B2
公开(公告)日:2021-08-10
申请号:US15691035
申请日:2017-08-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Tai-I Yang , Wei-Chen Chu , Li-Lin Su , Shin-Yi Yang , Cheng-Chi Chuang , Hsin-Ping Chen
IPC: H01L21/768 , H01L23/522 , H01L23/532
Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a conductive feature in a first dielectric layer. The semiconductor device structure also includes an etching stop layer over the first dielectric layer and a second dielectric layer over the etching stop layer. The semiconductor device structure further includes a conductive via in the etching stop layer and the second dielectric layer. In addition, the semiconductor device structure includes a conductive line over the conductive via. The semiconductor device structure also includes a first barrier liner covering the bottom surface of the conductive line. The semiconductor device structure further includes a second barrier liner surrounding sidewalls of the conductive line and the conductive via. The conductive line and the conductive via are confined in the first barrier liner and the second barrier liner.
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