公开(公告)号：US12278287B2

公开(公告)日：2025-04-15

申请号：US18175346

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US12166074B2

公开(公告)日：2024-12-10

申请号：US17651869

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Hsiang-Pi Chang ,  Huang-Lin Chao ,  Chung-Liang Cheng ,  Chi On Chui ,  Kun-Yu Lee ,  Tzer-Min Shen ,  Yen-Tien Tung ,  Chun-I Wu

IPC: H01L21/00 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

公开(公告)号：US20240379777A1

公开(公告)日：2024-11-14

申请号：US18783848

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/285 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer forming a gate stack.

公开(公告)号：US12132091B2

公开(公告)日：2024-10-29

申请号：US17532062

申请日：2021-11-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Liang Cheng ,  Ziwei Fang ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/823431 ,  H01L21/823443 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

公开(公告)号：US20240332091A1

公开(公告)日：2024-10-03

申请号：US18128119

申请日：2023-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shen-Yang LEE ,  Hsiang-Pi Chang ,  Huiching Chang ,  Shao An Wang ,  Kenichi Sano ,  Huang-Lin Chao

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66439 ,  H01L29/775

Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions in the gate openings, depositing a diffusion barrier layer on the oxide layers, depositing a first dielectric layer on the diffusion barrier layer, performing a doping process on the diffusion barrier layer and the first dielectric layer to form a doped diffusion barrier layer and a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.

公开(公告)号：US11925033B2

公开(公告)日：2024-03-05

申请号：US17217000

申请日：2021-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Liang Liu ,  Sheng-Chau Chen ,  Chung-Liang Cheng ,  Chia-Shiung Tsai ,  Yeong-Jyh Lin ,  Pinyen Lin ,  Huang-Lin Chao

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/285 ,  H01L29/06 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B61/22 ,  H01L21/02603 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

公开(公告)号：US11594633B2

公开(公告)日：2023-02-28

申请号：US17328145

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Chi On Chui ,  Huang-Lin Chao

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

公开(公告)号：US11581416B1

公开(公告)日：2023-02-14

申请号：US17406879

申请日：2021-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Pi Chang ,  Chung-Liang Cheng ,  I-Ming Chang ,  Yao-Sheng Huang ,  Huang-Lin Chao

IPC: H01L29/51 ,  H01L29/78 ,  H01L21/3115 ,  H01L21/8234 ,  H01L29/40

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.

公开(公告)号：US20230020099A1

公开(公告)日：2023-01-19

申请号：US17648152

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui ,  Chun-I Wu ,  Huang-Lin Chao

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/49 ,  H01L21/285 ,  H01L21/28

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, depositing a metal-containing layer over the gate dielectric layer, and depositing a silicon-containing layer on the metal-containing layer. The metal-containing layer and the silicon-containing layer in combination act as a work-function layer. A planarization process is performed to remove excess portions of the silicon-containing layer, the metal-containing layer, and the gate dielectric layer, with remaining portions of the silicon-containing layer, the silicon-containing layer, and the gate dielectric layer forming a gate stack.

公开(公告)号：US11164956B2

公开(公告)日：2021-11-02

申请号：US16548918

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Hsiang Lin ,  Teng-Chun Tsai ,  Akira Mineji ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/321 ,  H01L29/78

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.