公开(公告)号：US20240379800A1

公开(公告)日：2024-11-14

申请号：US18782176

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US20240282772A1

公开(公告)日：2024-08-22

申请号：US18302948

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting Chung ,  Jin Cai ,  Szuya Liao

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method includes forming a complementary Field-Effect Transistor (CFET) including a first FinFET and a second FinFET. The processes for forming the first FinFET includes forming at least one semiconductor fin having a first total count, and forming a first gate stack on the at least one semiconductor fin. The second FinFET is vertically aligned to the first FinFET. The processes for forming the second FinFET includes forming a plurality of semiconductor fins, wherein the plurality of semiconductor fins have a second total count greater than the first total count, and forming a second gate stack on the plurality of semiconductor fins.

公开(公告)号：US20230387310A1

公开(公告)日：2023-11-30

申请号：US18447453

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Ho ,  Ming-Shiang Lin ,  Jin Cai

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L29/517 ,  H01L29/66795 ,  H01L21/02181 ,  H01L21/02321

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) appl

公开(公告)号：US20230387235A1

公开(公告)日：2023-11-30

申请号：US18365995

申请日：2023-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/66545 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/0665

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US11183584B2

公开(公告)日：2021-11-23

申请号：US16746127

申请日：2020-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan Hsiao ,  Tung Ying Lee ,  Wei-Sheng Yun ,  Jin Cai

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction. Each of the first semiconductor layers at the first portion of the first semiconductor layers have a substantially same thickness.

公开(公告)号：US20200273997A1

公开(公告)日：2020-08-27

申请号：US16874539

申请日：2020-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng Yuan ,  Ming-Shiang Lin ,  Chia-Cheng Ho ,  Jin Cai ,  Tzu-Chung Wang ,  Tung Ying Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234

Abstract: The various described embodiments provide a transistor with a negative capacitance, and a method of creating the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of its thickness.

公开(公告)号：US11955527B2

公开(公告)日：2024-04-09

申请号：US17351622

申请日：2021-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Yi-Tse Hung ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Lain-Jong Li ,  Jin Cai

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/2003 ,  H01L29/66446 ,  H01L29/66545 ,  H01L29/78696

Abstract: A method includes forming a first sacrificial layer over a substrate, and forming a sandwich structure over the first sacrificial layer. The sandwich structure includes a first isolation layer, a two-dimensional material over the first isolation layer, and a second isolation layer over the two-dimensional material. The method further includes forming a second sacrificial layer over the sandwich structure, forming a first source/drain region and a second source/drain region on opposing ends of, and contacting sidewalls of, the two-dimensional material, removing the first sacrificial layer and the second sacrificial layer to generate spaces, and forming a gate stack filling the spaces.

公开(公告)号：US11443803B2

公开(公告)日：2022-09-13

申请号：US17095664

申请日：2020-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi Wu ,  Win-San Khwa ,  Jin Cai ,  Yu-Sheng Chen

IPC: G11C13/00

Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.

公开(公告)号：US20210366819A1

公开(公告)日：2021-11-25

申请号：US16881005

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Jin Cai ,  Yu-Sheng Chen

IPC: H01L23/50 ,  H01L23/44 ,  H01L21/82

Abstract: Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.

公开(公告)号：US10163621B1

公开(公告)日：2018-12-25

申请号：US15609775

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jin Cai

IPC: H01G4/018 ,  H01L21/02 ,  H01L29/66 ,  H01L33/00 ,  H01L27/088 ,  H01L31/113 ,  H01L21/8238 ,  H01L29/02

Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.