公开(公告)号：US20210202727A1

公开(公告)日：2021-07-01

申请号：US17204517

申请日：2021-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Ching-Wei Tsai ,  Wang-Chun Huang ,  Kuan-Lun Cheng

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

公开(公告)号：US20240379849A1

公开(公告)日：2024-11-14

申请号：US18783087

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US20240339526A1

公开(公告)日：2024-10-10

申请号：US18750379

申请日：2024-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US11296082B2

公开(公告)日：2022-04-05

申请号：US16947377

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

公开(公告)号：US10971609B2

公开(公告)日：2021-04-06

申请号：US16549266

申请日：2019-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Ching-Wei Tsai ,  Wang-Chun Huang ,  Kuan-Lun Cheng

IPC: H01L29/775 ,  H01L23/522 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768

Abstract: An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The method includes forming a first layer of metal lines of a first back end of line (BEOL) interconnect structure and forming a semiconductor nanowire structure on a first metal line of the first layer of metal lines. The BEOL interconnect structure is formed on a front end of line (FEOL) device layer having multiple active devices. The method further includes forming a first dielectric layer wrapped around the semiconductor nanowire structure, forming a metal layer on the dielectric layer and on a second metal line of the first layer of metal lines, and forming a second layer of metal lines of a second BEOL interconnect structure on the semiconductor nanowire structure. The first and second metal lines are electrically isolated from each other.

公开(公告)号：US12166036B2

公开(公告)日：2024-12-10

申请号：US18341081

申请日：2023-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

公开(公告)号：US12021136B2

公开(公告)日：2024-06-25

申请号：US18361556

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0669

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

公开(公告)号：US11688736B2

公开(公告)日：2023-06-27

申请号：US17657941

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Yang Chuang ,  Jia-Chuan You ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/7855

Abstract: A method of fabricating a semiconductor device includes providing a dummy structure having a plurality of channel layers, an inner spacer disposed between adjacent channels of the plurality of channel layers and at a lateral end of the channel layers, and a gate structure including a gate dielectric layer and a metal layer interposing the plurality of channel layers. The dummy structure is disposed at an active edge adjacent to an active region. A metal gate etching process is performed to remove the metal layer from the gate structure while the gate dielectric layer remains disposed at a channel layer-inner spacer interface. After performing the metal gate etching process, a dry etching process is performed to form a cut region along the active edge. The gate dielectric layer disposed at the channel layer-inner spacer interface prevents the dry etching process from damaging a source/drain feature within the adjacent active region.

公开(公告)号：US11664451B2

公开(公告)日：2023-05-30

申请号：US17216241

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Wei Ju Lee ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.

公开(公告)号：US12148830B2

公开(公告)日：2024-11-19

申请号：US18324405

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chieh Yang ,  Wei Ju Lee ,  Li-Yang Chuang ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.