公开(公告)号：US10985020B2

公开(公告)日：2021-04-20

申请号：US16818013

申请日：2020-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L25/065 ,  H01L25/07 ,  H01L23/535 ,  G03F7/20 ,  H01L21/8234

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

公开(公告)号：US20200126785A1

公开(公告)日：2020-04-23

申请号：US16190757

申请日：2018-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

公开(公告)号：US10535730B2

公开(公告)日：2020-01-14

申请号：US15964636

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20190109189A1

公开(公告)日：2019-04-11

申请号：US16199483

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L29/10 ,  H01L23/528

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

公开(公告)号：US11424359B2

公开(公告)日：2022-08-23

申请号：US17142618

申请日：2021-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US10964781B2

公开(公告)日：2021-03-30

申请号：US16199483

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/8605

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

公开(公告)号：US10665455B2

公开(公告)日：2020-05-26

申请号：US16190757

申请日：2018-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chen Lu ,  Ming-Chang Hsieh ,  Yi-Min Chen

IPC: H01L21/027 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  G03F7/20 ,  H01L21/8234

Abstract: In some embodiments, a method for forming an integrated circuit is provided. The method includes forming a first layer over a semiconductor wafer, the first layer having a first portion and a second portion. The first portion is patterned by projecting a first image field over the first portion of the first layer, where the first portion of the first layer corresponds to the first image field. The second portion is patterned by projecting a second image field over the second portion of the first layer, where the second portion of the first layer corresponds to the second image field. A second layer is formed over the first layer. The second layer is patterned by projecting a third image field over the second layer, where the third image field covers a majority of the first portion and a majority of the second portion of the first layer.

公开(公告)号：US11776901B2

公开(公告)日：2023-10-03

申请号：US17197381

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsien Hsieh ,  Yu-Hsing Chang ,  Yi-Min Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L23/53223 ,  H01L23/53295

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

公开(公告)号：US20220293515A1

公开(公告)日：2022-09-15

申请号：US17197381

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsien Hsieh ,  Yu-Hsing Chang ,  Yi-Min Chen

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.

公开(公告)号：US11145709B2

公开(公告)日：2021-10-12

申请号：US16439636

申请日：2019-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hong-Yang Chen ,  Tian Sheng Lin ,  Yi-Cheng Chiu ,  Hung-Chou Lin ,  Yi-Min Chen ,  Kuo-Ming Wu ,  Chiu-Hua Chung

IPC: H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L49/02 ,  H01L27/01 ,  H01L27/06

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.