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    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD
    1.
    发明公开
    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD 审中-公开

    公开(公告)号：US20230198529A1

    公开(公告)日：2023-06-22

    申请号：US18169119

    申请日：2023-02-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    CPC分类号： H03L7/085 ,  H03L7/0814

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    Delay estimation device and delay estimation method
    3.
    发明授权
    Delay estimation device and delay estimation method 有权

    公开(公告)号：US11616508B2

    公开(公告)日：2023-03-28

    申请号：US17529282

    申请日：2021-11-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD
    4.
    发明申请
    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD 有权

    公开(公告)号：US20220077861A1

    公开(公告)日：2022-03-10

    申请号：US17529282

    申请日：2021-11-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    Delay estimation device and delay estimation method
    5.
    发明授权
    Delay estimation device and delay estimation method 有权

    公开(公告)号：US11184009B2

    公开(公告)日：2021-11-23

    申请号：US17083304

    申请日：2020-10-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD
    6.
    发明申请
    DELAY ESTIMATION DEVICE AND DELAY ESTIMATION METHOD 有权

    公开(公告)号：US20210305988A1

    公开(公告)日：2021-09-30

    申请号：US17083304

    申请日：2020-10-29

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    Delay estimation device and delay estimation method
    8.
    发明授权
    Delay estimation device and delay estimation method 有权

    公开(公告)号：US11888490B2

    公开(公告)日：2024-01-30

    申请号：US18169119

    申请日：2023-02-14

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Tso Lin ,  Chin-Ming Fu ,  Mao-Ruei Li

    IPC分类号： H03L7/085 ,  H03L7/081

    CPC分类号： H03L7/085 ,  H03L7/0814

    摘要： The disclosure provides a delay estimation device and a delay estimation method. The delay estimation device includes a pulse generator, a digitally controlled delay line (DCDL), a time-to-digital converter (TDC), and a control circuit. The pulse generator receives a reference clock signal, outputs a first clock signal in response to a first rising edge of the reference clock signal, and outputs a second clock signal in response to a second rising edge of the reference clock signal. The DCDL receives the first clock signal from the pulse generator and converts the first clock signal into phase signals based on a combination of delay line codes. The TDC samples the phase signals to generate a timing code based on the second clock signal. The control circuit estimates a specific delay between the first clock signal and the second clock signal based on the timing code.

    Circuit and method to enhance efficiency of semiconductor device
    9.
    发明授权
    Circuit and method to enhance efficiency of semiconductor device 有权

    公开(公告)号：US11264979B1

    公开(公告)日：2022-03-01

    申请号：US17069643

    申请日：2020-10-13

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Mao-Ruei Li ,  Ming Hsien Tsai ,  Ruey-Bin Sheen

    IPC分类号： H03K7/08 ,  G06F30/20 ,  G04F10/00 ,  H03K3/017 ,  H03K5/156 ,  H03L7/085 ,  H03L7/06 ,  G11C16/32

    摘要： A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.