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    Processing unit for a computer and a computer system incorporating such a processing unit
    1.
    发明授权
    Processing unit for a computer and a computer system incorporating such a processing unit 失效
    用于计算机的处理单元和包含这种处理单元的计算机系统

    公开(公告)号：US06216236B1

    公开(公告)日：2001-04-10

    申请号：US09188903

    申请日：1998-11-10

    申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

    发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

    IPC分类号： G06F1134

    CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

    摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

    摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

    Image monitoring method, image monitoring apparatus and storage media
    4.
    发明申请
    Image monitoring method, image monitoring apparatus and storage media 审中-公开

    公开(公告)号：US20060013441A1

    公开(公告)日：2006-01-19

    申请号：US11229687

    申请日：2005-09-20

    申请人： Chieko Onuma ,  Yoshiki Kobayashi ,  Hisao Oodawa ,  Hiroshi Shojima

    发明人： Chieko Onuma ,  Yoshiki Kobayashi ,  Hisao Oodawa ,  Hiroshi Shojima

    IPC分类号： G06K9/00

    CPC分类号： G08B13/19602 ,  G06T7/254 ,  G06T7/262 ,  G08B13/19606 ,  G08B13/19608 ,  G08B13/19671 ,  G08B13/19691

    摘要： In order to precisely detect abnormal objects by use of a low-cost arrangement at high speeds while avoiding unwanted influence of variations of a light source and/or regularly vibrating objects in the environment concerned, there are provided a means 4200 for subdividing an image being input from a camera into blocks, an object candidate extraction unit 4700 which is operable to compare image data of a frame to be processed and image data of its immediately preceding frame in units of blocks to thereby extract an abnormal object candidate in accordance with the presence or absence of edges and a longitude-to-lateral edge radio change rate, and an object judging unit 4800 for determining or “judging” whether the abnormal object candidate is a true abnormal object or not, wherein the object judging unit 4800 regards it as an abnormal object in cases where movement of the abnormal object candidate was traceable for a prespecified length of time period.

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06785172B2

    公开(公告)日：2004-08-31

    申请号：US10325931

    申请日：2002-12-23

    申请人： Yoshiki Kobayashi

    发明人： Yoshiki Kobayashi

    IPC分类号： G11C700

    CPC分类号： G11C29/32 ,  G11C2029/3202 ,  G11C2207/104

    摘要： In a semiconductor memory device according to the present invention, which allows a memory cell array unit and a memory circuit internal logic unit to be tested independently of each other, a first test circuit unit TCi1 to which an address signal a″, a scan-in signal SIN, a scan select signal SS and a shift clock signal SCLK are input, outputs an address signal a′″ and a scan-out signal SiOUT1. The address signal a′″ is input to the memory cell array unit MCA and a column selector CS, whereas the scan-out signal SiOUT1 is input to a second test circuit unit TCi2. The second test circuit unit TCi2, to which the scan-out signal SiOUT1, the scan select signal SS, a write control signal WCTRL and a scan clock signal SCLK are input, outputs at a scan-out signal SOUT. The first test circuit unit and the second test circuit unit each achieve a parallel/serial conversion function.

    摘要翻译： 在根据本发明的半导体存储器件中，允许独立地测试存储单元阵列单元和存储器电路内部逻辑单元的第一测试电路单元TCi1，地址信号a“，扫描 输入信号SIN，扫描选择信号SS和移位时钟信号SCLK，输出地址信号a“和扫描输出信号SiOUT1。 地址信号a“”被输入到存储单元阵列单元MCA和列选择器CS，而扫描输出信号SiOUT1被输入到第二测试电路单元TCi2。 扫描输出信号SiOUT1，扫描选择信号SS，写控制信号WCTRL和扫描时钟信号SCLK被输入的第二测试电路单元TCi2以扫描输出信号SOUT输出。 第一测试电路单元和第二测试电路单元各自实现并行/串行转换功能。

    System and method for preparing a recognition dictionary
    8.
    发明授权
    System and method for preparing a recognition dictionary 失效
    用于准备识别字典的系统和方法

    公开(公告)号：US4682365A

    公开(公告)日：1987-07-21

    申请号：US742559

    申请日：1985-06-07

    申请人： Miyahiko Orita ,  Yoshiki Kobayashi ,  Tadaaki Mishima

    发明人： Miyahiko Orita ,  Yoshiki Kobayashi ,  Tadaaki Mishima

    IPC分类号： G06T7/00 ,  G06K9/68

    CPC分类号： G06K9/6282

    摘要： For the preparation of a tree structure recognition dictionary, in order to obtain the best decision tree, the maximum depth or the sum of the depths should be taken into account. For this purpose, there is provided a system and method for preparing a recognition dictionary which makes it possible to shorten both the maximum recognition time and the total recognition time by successively allocating to nodes of the decision tree features, for which a feature evaluation measure called "maximum estimated depth" for reducing the maximum depth or "sum of estimated node numbers" for reducing the sum of the depths is the smallest.

    摘要翻译： 为了准备树结构识别字典，为了获得最佳决策树，应考虑最大深度或深度之和。 为此，提供了一种用于准备识别字典的系统和方法，其使得可以通过连续分配给决策树特征的节点来缩短最大识别时间和总识别时间两者，对于该决策树特征，称为特征评估度量 用于减小最大深度的“最大估计深度”或用于减小深度之和的“估计节点数之和”是最小的。

    Bus-coupler
    9.
    发明授权
    Bus-coupler 失效
    总线耦合器

    公开(公告)号：US3947818A

    公开(公告)日：1976-03-30

    申请号：US531161

    申请日：1974-12-09

    申请人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

    发明人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

    IPC分类号： G06F13/36 ,  G06F13/40 ,  H04L12/40 ,  H04L29/08 ,  H04Q9/00

    CPC分类号： G06F13/4036

    摘要： A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.

    摘要翻译： 用于连接多个总线的信息传输系统中的总线耦合器或总线窗口，其中多个运算单元，多个存储器或存储单元以及多个输入 - 输出单元通过站单独连接。 总线耦合器包括用于防止在总线之间的通信中可能发生的死锁的死锁控制电路。

    Semiconductor integrated circuit
    10.
    发明申请
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US20060048029A1

    公开(公告)日：2006-03-02

    申请号：US11206948

    申请日：2005-08-19

    申请人： Yoshiki Kobayashi

    发明人： Yoshiki Kobayashi

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318572

    摘要： The number of S-FFs in a scan-path is decreased by half and a test time needed is decreased. An I/O terminal 1A is connected to a scan-path 31-3m and a combination circuit 2 via a selector 5A and an output of the scan-path 31-3m is connected to an I/O terminal 1B via a selector 6A and a tri-state buffer 7A. The I/O terminal 1B is connected to a scan-path 3m+1-3n and to the combination circuit 2 via a selector 5B and the output of the scan-path 3m+1-3n is connected to the I/O terminal 1A via a selector 6B and tri-state buffer 7B. When testing, the tri-state buffers are turned off and test-data are supplied by connecting the I/O terminal 1A, 1B to the scan-path 31-3m, 3m+1-3n respectively. Thereafter, output signals of the combination circuit is applied to each S-FF 3, and the test data are read out from the I/O terminal 1A, 1B by turning on the each tri-state buffer 7A, 7B.

    摘要翻译： 扫描路径中的S-FF的数量减少一半，所需的测试时间减少。 I / O端子1A通过选择器5A连接到扫描路径3＆lt; 1＆gt;＆lt; 3＆gt;和组合电路2， 路径3通过选择器6A和三态缓冲器7A将I / O端子1B连接到I / O端子1B。I / O端子1 B通过选择器5B连接到扫描路径3＆lt; m + 1＆gt; - ＆lt; N＆gt;和组合电路2，并且扫描路径3的输出< 通过选择器6B和三态缓冲器7B连接到I / O端子1A。当测试时，三态缓冲器 被关闭，并且通过将I / O端子1A，1B连接到扫描路径3 3 3， 分别为m + 1 + 3 。 此后，组合电路的输出信号被施加到每个S-FF 3，并且通过接通每个三态缓冲器7A，7B从I / O端子1A，1B读出测试数据。