公开(公告)号：US3947818A

公开(公告)日：1976-03-30

申请号：US531161

申请日：1974-12-09

申请人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

发明人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Toshitaka Hara

IPC分类号： G06F13/36 ,  G06F13/40 ,  H04L12/40 ,  H04L29/08 ,  H04Q9/00

CPC分类号： G06F13/4036

摘要： A bus-coupler or bus window in an information transport system for connecting a plurality of buses, to each of which a plurality of arithmetic units, a plurality of memory or storage units and a plurality of input-output units are connected separately through stations. The bus coupler includes a dead-lock control circuit for preventing a dead-lock which could possibly occur in communication between the buses.

摘要翻译： 用于连接多个总线的信息传输系统中的总线耦合器或总线窗口，其中多个运算单元，多个存储器或存储单元以及多个输入 - 输出单元通过站单独连接。 总线耦合器包括用于防止在总线之间的通信中可能发生的死锁的死锁控制电路。

公开(公告)号：US5968160A

公开(公告)日：1999-10-19

申请号：US923632

申请日：1997-09-04

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80 ,  G06F15/16

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

摘要翻译： 具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备 同步。 分别对应于多个处理器元件提供多个并行操作控制设备。 数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。 共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

公开(公告)号：US3986169A

公开(公告)日：1976-10-12

申请号：US582147

申请日：1975-05-30

申请人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Jushi Ide ,  Toshiro Kamiuchi

发明人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Jushi Ide ,  Toshiro Kamiuchi

IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  G06F17/40 ,  G08B29/00

CPC分类号： G06F12/1433 ,  G06F15/161

摘要： In a multi-computer system having input/output devices for common use, protection is made for the devices upon transferring of the input/output data by comparing a device identifying number or address signal and a number signal identifying a central processor unit which demands the transfer of data, thereby to determine on the basis of the result of the comparison whether the data transfer between the device and the central processor unit is allowable. When the transfer is not admitted, the input/output operation of the device is inhibited.

摘要翻译： 在具有用于共同使用的输入/输出装置的多计算机系统中，通过比较设备识别号码或地址信号和识别要求中断处理器单元的中央处理器单元的数字信号来传送输入/输出数据，对设备进行保护 传送数据，从而根据比较结果确定设备与中央处理器单元之间的数据传输是否被允许。 当传输不被允许时，设备的输入/输出操作被禁止。

公开(公告)号：US5784630A

公开(公告)日：1998-07-21

申请号：US367928

申请日：1995-01-03

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

公开(公告)号：US4486834A

公开(公告)日：1984-12-04

申请号：US485020

申请日：1983-04-14

申请人： Yoshiki Kobayashi ,  Hideo Maejima ,  Tadaaki Bandoh ,  Hiroaki Nakanishi

发明人： Yoshiki Kobayashi ,  Hideo Maejima ,  Tadaaki Bandoh ,  Hiroaki Nakanishi

IPC分类号： G06F12/16 ,  G06F11/16 ,  G06F11/20 ,  G06F11/26 ,  G06F15/167 ,  G11C29/00 ,  G06F13/00 ,  G11C9/00

CPC分类号： G06F11/2082 ,  G06F11/26 ,  G06F15/167 ,  G11C29/74 ,  G06F11/2064

摘要： A multi-computer system having a dual common memory adapted to perform Read/Write operations by means of a plurality of computers. Each computer in the system consists of a central processing unit, a main memory and a dual memory access unit. The dual memory access unit is adapted to provide a status signal representative of whether the data from the common memory is correct or not and a maintenance signal representative of whether a maintenance operation is demanded. A memory access is made only to the common memory demanding the maintenance when the program run by the computer is a maintenance program, and only to the normal common memory during the usual operation.

摘要翻译： 一种具有适于通过多个计算机执行读/写操作的双公共存储器的多计算机系统。 系统中的每台计算机都由中央处理单元，主存储器和双存储器存取单元组成。 双存储器访问单元适于提供表示来自公共存储器的数据是否正确的状态信号，以及表示是否需要维护操作的维护信号。 只有当计算机运行的程序是维护程序时才需要进行维护的公共存储器的存储器访问，并且在正常操作期间仅对正常的公共存储器进行存储器访问。

公开(公告)号：US4095268A

公开(公告)日：1978-06-13

申请号：US712803

申请日：1976-08-09

申请人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Hideo Maejima ,  Hajime Yasuda

发明人： Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Hideo Maejima ,  Hajime Yasuda

IPC分类号： G06F9/22 ,  G06F9/00 ,  G06F9/46 ,  G06F11/28 ,  G06F11/32 ,  G06F1/04 ,  G06F3/02

CPC分类号： G06F9/461

摘要： In an electronic computer system wherein, when a microprogram-controlled central processing unit receives a stop signal from a console, the contents of a group of registers are assigned to predetermined fixed areas in a main memory and, in response to a start signal, the assigned contents of the group of registers are delivered from the fixed areas to the group of registers. The reading and writing of the contents of the group of registers within the central processing unit is effected for the fixed areas of the main memory in which the contents are assigned.

公开(公告)号：US06675311B2

公开(公告)日：2004-01-06

申请号：US10002444

申请日：2001-12-06

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F104

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.

摘要翻译： 一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生 至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件。 至少一对逻辑设备由时钟信号K1同步控制。

公开(公告)号：US5623626A

公开(公告)日：1997-04-22

申请号：US440692

申请日：1995-05-15

申请人： Michio Morioka ,  Tadaaki Bandoh ,  Masayuki Tanji

发明人： Michio Morioka ,  Tadaaki Bandoh ,  Masayuki Tanji

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/1045

摘要： A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.

摘要翻译： 逻辑高速缓存存储器具有逻辑标签和物理标签作为用于比较的地址标签，以及表示其状态的状态信息。 数据状态和块状态被登记在同一个入口位置。 当使用逻辑地址进行访问时，对逻辑标签进行访问以检测数据的存在，并且当使用物理地址进行访问时，使用不依赖于地址的偏移部分对物理标签进行访问 转换，检测数据的存在。

公开(公告)号：US4967339A

公开(公告)日：1990-10-30

申请号：US179554

申请日：1988-04-08

申请人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

发明人： Hiroaki Fukumaru ,  Soichi Takaya ,  Takayuki Morioka ,  Tadaaki Bandoh ,  Shinichiro Yamaguchi ,  Kenji Hirose

IPC分类号： G06F9/38 ,  G06F7/00 ,  G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F9/355

CPC分类号： G06F9/30014 ,  G06F9/342 ,  G06F9/3889

摘要： A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a way that a high order 32 bit operation is performed in an arithmetic device in the operand effective address unit and a low order 32 bit operation is performed in another arithmetic device in the instruction execution unit. A carry is transferred from the low order 32 bit arithmetic device to the high order 32 bit arithmetic device. The arithmetic devices thus joined can perform the 64 bit with data operation as an arithmetic device.

摘要翻译： 处理器通过操作数有效地址计算单元执行流水线并行处理，用于计算执行指令所需的操作数有效地址和执行指令的指令执行单元。 执行64位宽的数据操作，使得在操作数有效地址单元中的算术装置中执行高阶32位操作，并且在指令执行单元中的另一个运算装置中执行低位32位操作。 进位从低位32位运算器传输到高位32位运算器件。 如此连接的算术装置可以作为运算装置执行数据操作的64位。

公开(公告)号：US5506982A

公开(公告)日：1996-04-09

申请号：US278245

申请日：1994-07-21

申请人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

发明人： Takashi Hotta ,  Kozaburo Kurita ,  Masahiro Iwamura ,  Hideo Maejima ,  Shigeya Tanaka ,  Tadaaki Bandoh ,  Yasuhiro Nakatsuka ,  Kazuo Kato ,  Sin-ichi Sinoda

IPC分类号： G06F1/10 ,  H03K5/156 ,  H03L7/18 ,  G06F1/06

CPC分类号： H03K5/1565 ,  G06F1/10 ,  H03L7/18

摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.