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    Processing unit for a computer and a computer system incorporating such a processing unit
    1.
    发明授权
    Processing unit for a computer and a computer system incorporating such a processing unit 失效
    用于计算机的处理单元和包含这种处理单元的计算机系统

    公开(公告)号：US06216236B1

    公开(公告)日：2001-04-10

    申请号：US09188903

    申请日：1998-11-10

    申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

    发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

    IPC分类号： G06F1134

    CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

    摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

    摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

    Current control semiconductor element and control device using the same
    4.
    发明授权
    Current control semiconductor element and control device using the same 有权
    电流控制半导体元件及使用其的控制装置

    公开(公告)号：US08653601B2

    公开(公告)日：2014-02-18

    申请号：US13807278

    申请日：2011-06-02

    申请人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

    发明人： Teppei Hirotsu ,  Nobuyasu Kanekawa ,  Itaru Tanabe

    IPC分类号： H01L21/8234 ,  H01L29/76 ,  H02M3/24

    CPC分类号： H01L27/088 ,  H01L27/0211 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4238 ,  H03K17/145

    摘要： This invention provides a current control semiconductor element in which dependence of a sense ratio on a temperature distribution is eliminated and the accuracy of current detection using a sense MOSFET can be improved, and to provide a control device using the current control semiconductor element. The current control semiconductor element 1 includes a main MOSFET 7 that drives a current and a sense MOSFET 8 that is connected to the main MOSFET in parallel and detects a current shunted from a current of the main MOSFET. The main MOSFET is formed using a multi-finger MOSFET that has a plurality of channels and is arranged in a row. When a distance between the center of the multi-finger MOSFET 7 and a channel located farthest from the center of the multi-finger MOSFET 7 is indicated by L, a channel that is located closest to a position distant by a distance of (L/(√3)) from the center of the multi-finger MOSFET is used as a channel for the sense MOSFET 8.

    摘要翻译： 本发明提供了一种电流控制半导体元件，其中消除了感测比对温度分布的依赖性，并且可以提高使用感测MOSFET的电流检测的精度，并提供使用电流控制半导体元件的控制装置。 电流控制半导体元件1包括驱动电流的主MOSFET 7和并联连接到主MOSFET的感测MOSFET 8，并且检测从主MOSFET的电流分流的电流。 主MOSFET使用具有多个通道并排列成一排的多指MOSFET形成。 当多指MOSFET 7的中心与距离多指MOSFET 7的中心最远的通道之间的距离由L表示时，位于最靠近距离为（L / （√3））从多指MOSFET的中心用作感测MOSFET 8的通道。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR OPERATING SAME
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR OPERATING SAME 有权
    半导体集成电路及其工作方法

    公开(公告)号：US20140032860A1

    公开(公告)日：2014-01-30

    申请号：US14110786

    申请日：2011-04-21

    申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

    发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

    IPC分类号： G06F12/02

    CPC分类号： G06F12/02 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/1687 ,  G06F2201/845

    摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

    摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

    COMPUTER SYSTEM
    6.
    发明申请
    COMPUTER SYSTEM 有权
    电脑系统

    公开(公告)号：US20110283033A1

    公开(公告)日：2011-11-17

    申请号：US13106788

    申请日：2011-05-12

    申请人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    发明人： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    IPC分类号： G06F13/24 ,  G06F13/26

    CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

    摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

    摘要翻译： 提供了一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。

    Electric Power Steering Controller and Electric Power Steering System
    7.
    发明申请
    Electric Power Steering Controller and Electric Power Steering System 审中-公开
    电动转向控制器和电动助力转向系统

    公开(公告)号：US20110218704A1

    公开(公告)日：2011-09-08

    申请号：US13033653

    申请日：2011-02-24

    申请人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki

    发明人： Nobuyasu Kanekawa ,  Ryoichi Kobayashi ,  Tomonobu Koseki

    IPC分类号： G06F19/00 ,  B62D5/04

    CPC分类号： B62D5/049 ,  B62D5/0484

    摘要： The present invention provides an electric power steering controller and an electric power steering system that allow appropriate operation even when the operation of their torque sensors is abnormal.The controller 100 of a main microcomputer 1-1 outputs motor drive signals 3 to a drive circuit 5 based on first and second torque signals detected by a torque sensor 2 that detects steering force. The drive circuit 5 drives a motor 6 to generate assistive torque. A torque sensor abnormality detector 101 is installed within the main microcomputer 1-1 and detects abnormalities of the torque sensor 2 based on the first and second torque signals. An excessive torque detector 102 is installed within an external device 1-2 and outputs a motor stop signal when either of the first and second torque signals exceeds a given value.

    摘要翻译： 本发明提供了一种电动助力转向控制器和电动助力转向系统，其即使在其扭矩传感器的操作异常时也允许适当的操作。 主微型计算机1-1的控制器100基于检测转向力的转矩传感器2检测到的第一和第二转矩信号将电动机驱动信号3输出到驱动电路5。 驱动电路5驱动马达6产生辅助转矩。 转矩传感器异常检测器101安装在主微型计算机1-1内，并基于第一和第二转矩信号检测转矩传感器2的异常。 过大的转矩检测器102安装在外部装置1-2内，并且当第一和第二转矩信号中的任何一个超过给定值时，输出电动机停止信号。

    Distributed Control System
    10.
    发明申请
    Distributed Control System 有权
    分布式控制系统

    公开(公告)号：US20090089627A1

    公开(公告)日：2009-04-02

    申请号：US12194575

    申请日：2008-08-20

    申请人： Masahiro Matsubara ,  Kohei Sakurai ,  Kotaro Shimamura ,  Nobuyasu Kanekawa

    发明人： Masahiro Matsubara ,  Kohei Sakurai ,  Kotaro Shimamura ,  Nobuyasu Kanekawa

    IPC分类号： G06F11/00

    CPC分类号： G06F11/182 ,  G06F11/0709 ,  G06F11/076 ,  H04L41/0677

    摘要： There is provided a distributed system having a plurality of nodes connected by a network. Each of the nodes includes: a common-parameter-value determining unit for determining a common-parameter-value from values of a parameter (each value being possessed by a corresponding one of the nodes); a common-operation execution unit for executing a common-operation using, as its input, a value of the parameter or the common-parameter-value; a send/receive unit for exchanging, via the network, the parameter values used for the determination of the common-parameter-value and the results of the common-operation execution with the other nodes; and a fault identification unit that compares the common-operation execution results collected from all the nodes and determines that an error occurs if not all the results are the same.

    摘要翻译： 提供了具有通过网络连接的多个节点的分布式系统。 每个节点包括：公共参数值确定单元，用于根据参数的值（由相应的一个节点拥有的每个值）确定公共参数值; 公共执行单元，用于使用参数或公共参数值的值作为其输入来执行公共操作; 用于经由网络交换用于确定公共参数值的参数值和与其他节点的共同操作执行结果的发送/接收单元; 以及故障识别单元，其比较从所有节点收集的共同操作执行结果，并且如果不是全部结果相同，则确定出现错误。