公开(公告)号：US20120097980A1

公开(公告)日：2012-04-26

申请号：US13381605

申请日：2011-02-07

申请人： Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

发明人： Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

IPC分类号： H01L29/24 ,  H01L21/265

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66068

摘要： A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.

摘要翻译： 碳化硅绝缘栅型半导体器件的端接构造包括具有第一主面，栅电极和源极互连的第一导电类型的半导体层以及周向复原区域。 半导体层包括第二导电类型的主体区域，第一导电类型的源极区域，第二导电类型的接触区域和第二导电类型的周边复原区域。 除了身体区域之外的圆周清理区域的一部分的宽度大于或等于至少半导体层的厚度的1/2。 可以提供具有高击穿电压和高性能的碳化硅绝缘栅型半导体器件。

公开(公告)号：US20120056202A1

公开(公告)日：2012-03-08

申请号：US13320247

申请日：2010-04-27

申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

IPC分类号： H01L29/24

CPC分类号： H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A MOSFET, which is a semiconductor device allowing for reduced on-resistance while restraining stacking faults from being produced due to heat treatment in a device manufacturing process, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source contact electrode disposed on the active layer; and a drain electrode formed on the other main surface of the silicon carbide substrate. The silicon carbide substrate includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. Further, the base layer has an impurity concentration greater than 2×1019 cm−3, and the SiC layer has an impurity concentration greater than 5×1018 cm−3 and smaller than 2×1019 cm−3.

摘要翻译： 一种MOSFET，其是在器件制造工艺中由于热处理而允许抑制堆垛层错而产生降低的导通电阻的半导体器件，包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在有源层上的源极接触电极; 以及形成在碳化硅衬底的另一个主表面上的漏电极。 碳化硅基板包括：由碳化硅制成的基层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 此外，基底层的杂质浓度大于2×1019cm-3，并且SiC层的杂质浓度大于5×1018cm-3且小于2×1019cm-3。

公开(公告)号：US20110175110A1

公开(公告)日：2011-07-21

申请号：US13120890

申请日：2010-03-23

申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/24 ,  H01L21/336 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： A MOSFET includes a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. When the insulating film has a thickness of not less than 30 nm and not more than 46 nm, the threshold voltage thereof is not more than 2.3V. When the insulating film has a thickness of more than 46 nm and not more than 100 nm, the threshold voltage thereof is more than 2.3 V and not more than 4.9 V.

摘要翻译： MOSFET包括碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 当绝缘膜的厚度不小于30nm且不大于46nm时，其阈值电压不大于2.3V。 当绝缘膜的厚度大于46nm且不大于100nm时，其阈值电压大于2.3V且不大于4.9V。

公开(公告)号：US08610131B2

公开(公告)日：2013-12-17

申请号：US13435863

申请日：2012-03-30

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC分类号： H01L29/15

CPC分类号： H01L29/7397 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.

摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为 相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触 在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

公开(公告)号：US20120248462A1

公开(公告)日：2012-10-04

申请号：US13435863

申请日：2012-03-30

申请人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

发明人： Keiji Wada ,  Takeyoshi Masuda ,  Misako Honaga ,  Toru Hiyoshi

IPC分类号： H01L29/739

CPC分类号： H01L29/7397 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068

摘要： An IGBT includes a groove provided in a silicon carbide semiconductor layer, a body region of a first conductivity type provided in the silicon carbide semiconductor layer, and an insulating film covering at least a sidewall surface of the groove, the sidewall surface of the groove being a surface having an off angle of 50° or more and 65° or less with respect to a {0001} plane, the sidewall surface of the groove including a surface of the body region, the insulating film being in contact with at least the surface of the body region at the sidewall surface of the groove, and a first conductivity type impurity concentration in the body region being 5×1016 cm−3 or more.

摘要翻译： IGBT包括设置在碳化硅半导体层中的沟槽，设置在碳化硅半导体层中的第一导电类型的主体区域以及至少覆盖该沟槽的侧壁表面的绝缘膜，槽的侧壁表面为 相对于{0001}面具有偏离角度为50°以上且65°以下的表面，所述凹槽的侧壁表面包括所述主体区域的表面，所述绝缘膜至少与所述表面接触 在所述槽的侧壁面的所述主体区域中，所述体区的第一导电型杂质浓度为5×10 16 cm -3以上。

公开(公告)号：US20120228640A1

公开(公告)日：2012-09-13

申请号：US13512456

申请日：2011-07-14

申请人： Takeyoshi Masuda ,  Shin Harada ,  Misako Honaga ,  Keiji Wada ,  Toru Hiyoshi

发明人： Takeyoshi Masuda ,  Shin Harada ,  Misako Honaga ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/66068 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/6606 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/8613 ,  H01L29/868

摘要： There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes: a substrate having a main surface; and a silicon carbide layer formed on the main surface of the substrate and including a side surface inclined relative to the main surface. The side surface substantially includes a {03-3-8} plane. The side surface includes a channel region.

摘要翻译： 提供了具有稳定特性的高质量半导体器件和制造这种半导体器件的方法。 半导体器件包括：具有主表面的衬底; 以及形成在所述基板的主表面上并且包括相对于所述主表面倾斜的侧表面的碳化硅层。 侧表面基本上包括{03-3-8}平面。 侧面包括通道区域。

公开(公告)号：US20120007104A1

公开(公告)日：2012-01-12

申请号：US13255031

申请日：2010-04-22

申请人： Keiji Wada ,  Hideto Tamaso ,  Takeyoshi Masuda ,  Misako Honaga

发明人： Keiji Wada ,  Hideto Tamaso ,  Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/7802 ,  H01L21/0455 ,  H01L21/0485 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/808

摘要： A semiconductor device employing silicon carbide, and the like are provided. In the semiconductor device, even when an electrode material and an upper electrode material are different, a problem does not take place at an interface at which these different types of metals are in contact with each other, thus obtaining high reliability in long-term use.The semiconductor device includes: a contact electrode 16 in contact with silicon carbides 14, 18; and an upper electrode 19 electrically conductive to the contact electrode. The contact electrode 16 is formed of an alloy including titanium, aluminum, and silicon, the upper electrode 19 is formed of aluminum or an aluminum alloy, and the upper electrode achieves the electric conduction to the contact electrode with the upper electrode making contact with the contact electrode.

摘要翻译： 提供了使用碳化硅的半导体器件等。 在半导体装置中，即使电极材料和上部电极材料不同，在这些不同类型的金属彼此接触的界面处也不会发生问题，因此在长期使用中获得高可靠性 。 半导体器件包括：与碳化硅14,18接触的接触电极16; 以及与接触电极导电的上电极19。 接触电极16由包括钛，铝和硅的合金形成，上电极19由铝或铝合金形成，上电极实现与接触电极的导电，上电极与 接触电极。

公开(公告)号：US08901568B2

公开(公告)日：2014-12-02

申请号：US13381605

申请日：2011-02-07

申请人： Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

发明人： Takeyoshi Masuda ,  Keiji Wada ,  Misako Honaga

IPC分类号： H01L29/24 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/66068

摘要： A termination configuration of a silicon carbide insulating gate type semiconductor device includes a semiconductor layer of a first conductivity type having a first main face, a gate electrode, and a source interconnection, as well as a circumferential resurf region. The semiconductor layer includes a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential resurf region of the second conductivity type. A width of a portion of the circumferential resurf region excluding the body region is greater than or equal to ½ the thickness of at least the semiconductor layer. A silicon carbide insulating gate type semiconductor device of high breakdown voltage and high performance can be provided.

摘要翻译： 碳化硅绝缘栅型半导体器件的端接构造包括具有第一主面，栅电极和源极互连的第一导电类型的半导体层以及周向复原区域。 半导体层包括第二导电类型的主体区域，第一导电类型的源极区域，第二导电类型的接触区域和第二导电类型的周边复原区域。 除了身体区域之外的圆周清理区域的一部分的宽度大于或等于至少半导体层的厚度的1/2。 可以提供具有高击穿电压和高性能的碳化硅绝缘栅型半导体器件。

公开(公告)号：US08648349B2

公开(公告)日：2014-02-11

申请号：US13121122

申请日：2010-05-12

申请人： Takeyoshi Masuda ,  Misako Honaga

发明人： Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/66909 ,  H01L29/8083

摘要： A MOSFET which is a semiconductor device capable of achieving a stable reverse breakdown voltage and reduced on-resistance includes a SiC wafer of an n conductivity type, a plurality of p bodies of a p conductivity type formed to include a first main surface of the SiC wafer, and n+ source regions of the n conductivity type formed in regions surrounded by the plurality of p bodies, respectively, when viewed two-dimensionally. Each of the p bodies has a circular shape when viewed two-dimensionally, and each of the n+ source regions is arranged concentrically with each of the p bodies and has a circular shape when viewed two-dimensionally. Each of the plurality of p bodies is arranged to be positioned at a vertex of a regular hexagon when viewed two-dimensionally.

摘要翻译： 作为能够实现稳定的反向击穿电压和降低的导通电阻的半导体器件的MOSFET包括n导电型的SiC晶片，形成为包括SiC晶片的第一主表面的多个p导电类型的多个p体 ，以及分别形成在由多个p体包围的区域中的n导电类型的n +源极区域。 每个p体在二维观察时具有圆形形状，并且n +源区域中的每一个与每个p体同心地布置，并且在二维观察时具有圆形形状。 当二维观察时，多个p体中的每一个被布置成定位在正六边形的顶点处。

公开(公告)号：US08564017B2

公开(公告)日：2013-10-22

申请号：US13485423

申请日：2012-05-31

申请人： Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

发明人： Misako Honaga ,  Takeyoshi Masuda ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/66 ,  H01L21/337 ,  H01L29/15

CPC分类号： H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66068

摘要： A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j−N2j>N1d and N2j

摘要翻译： 漂移层具有电流流动的厚度方向，并具有用于第一导电类型的杂质浓度N1d。 身体区域设置在漂移层的一部分上，具有由栅电极切换的通道，具有用于第一导电类型的杂质浓度N1b，并且具有大于杂质的第二导电类型的杂质浓度N2b 浓度N1b。 JFET区域与漂移层上的体区附近配置，对于第一导电类型具有杂质浓度N1j，并且对于第二导电类型的杂质浓度N2j小于杂质浓度N1j。 N1j-N2j> N1d和N2j