公开(公告)号：US08643065B2

公开(公告)日：2014-02-04

申请号：US12919992

申请日：2009-12-11

申请人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

发明人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

IPC分类号： H01L29/80

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

公开(公告)号：US20120208302A1

公开(公告)日：2012-08-16

申请号：US13502991

申请日：2011-02-25

申请人： Satomi Itoh ,  Hiromu Shiomi ,  Yasuo Namikawa ,  Keiji Wada ,  Mitsuru Shimazu ,  Toru Hiyoshi

发明人： Satomi Itoh ,  Hiromu Shiomi ,  Yasuo Namikawa ,  Keiji Wada ,  Mitsuru Shimazu ,  Toru Hiyoshi

IPC分类号： H01L21/66

CPC分类号： H01L21/02057 ,  H01L21/02236 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802

摘要： There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.

摘要翻译： 提供了一种制造提高性能的SiC半导体器件的方法。 SiC半导体器件的制造方法包括以下步骤。 也就是说，制备具有至少一部分注入有杂质的第一表面的SiC半导体。 通过清洗SiC半导体的第一表面，形成第二表面。 在第二表面上形成含Si膜。 通过氧化含Si膜，形成构成SiC半导体器件的氧化物膜。

公开(公告)号：US20120161157A1

公开(公告)日：2012-06-28

申请号：US13393235

申请日：2010-09-28

申请人： Hiroki Inoue ,  Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

发明人： Hiroki Inoue ,  Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

IPC分类号： H01L29/161

CPC分类号： H01L29/7802 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02444 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02631 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/66068

摘要： A silicon carbide substrate, which achieves restrained warpage even when a different-type material layer made of a material other than silicon carbide, includes: a base layer made of silicon carbide; and a plurality of SiC layers arranged side by side on the base layer when viewed in a planar view and each made of single-crystal silicon carbide. A gap is formed between end surfaces of adjacent SiC layers.

摘要翻译： 即使当由不同于碳化硅的材料制成的不同类型的材料层时也能实现约束翘曲的碳化硅衬底包括：由碳化硅制成的基底层; 以及在平面图中观察时，在基底层上并排设置的多个SiC层，并且均由单晶碳化硅构成。 在相邻SiC层的端面之间形成间隙。

公开(公告)号：US20120126251A1

公开(公告)日：2012-05-24

申请号：US13388691

申请日：2011-02-25

申请人： Makoto Sasaki ,  Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Hiroki Inoue ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa ,  Taku Horii

发明人： Makoto Sasaki ,  Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Hiroki Inoue ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa ,  Taku Horii

IPC分类号： H01L29/24 ,  H01L21/04

CPC分类号： H01L29/7802 ,  H01L21/2007 ,  H01L21/3247 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

摘要： A method for manufacturing a silicon carbide substrate achieves reduced manufacturing cost. The method includes the steps of: preparing a base substrate and a SiC substrate; fabricating a stacked substrate by stacking the base substrate and the SiC substrate; fabricating a connected substrate by heating the stacked substrate; transferring a void, formed at a connection interface, in a thickness direction of the connected substrate by heating the connected substrate to cause the base substrate to have a temperature higher than that of the SiC substrate; and removing the void by removing a region including a main surface of the base substrate opposite to the SiC substrate.

摘要翻译： 制造碳化硅衬底的方法降低了制造成本。 该方法包括以下步骤：制备基底和SiC衬底; 通过堆叠基底基板和SiC基板来制造堆叠的基板; 通过加热堆叠的基板来制造连接的基板; 通过加热连接的基板，在连接的基板的厚度方向上形成在连接界面处形成的空隙，使得基底基板的温度高于SiC基板的温度; 并且通过去除包括与SiC衬底相对的基底衬底的主表面的区域来去除空隙。

公开(公告)号：US20120061687A1

公开(公告)日：2012-03-15

申请号：US13319599

申请日：2010-04-27

申请人： Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

发明人： Shin Harada ,  Makoto Sasaki ,  Taro Nishiguchi ,  Yasuo Namikawa ,  Shinsuke Fujiwara

IPC分类号： H01L29/16

CPC分类号： H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： A silicon carbide substrate, which allows for reduced resistivity in the thickness direction thereof while restraining stacking faults from being produced due to heat treatment, includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on one main surface of the base layer. The base layer has an impurity concentration greater than 2×1019 cm−3. Further, the SiC layer has an impurity concentration greater than 5×1018 cm−3 and smaller than 2×1019 cm−3.

摘要翻译： 一种碳化硅衬底，其允许在其抑制由于热处理而产生的堆垛层错的同时在其厚度方向上具有降低的电阻率，包括：由碳化硅制成的基底层; 以及由单晶碳化硅制成并设置在基层的一个主表面上的SiC层。 基层的杂质浓度大于2×10 19 cm -3。 此外，SiC层的杂质浓度大于5×10 18 cm -3，小于2×10 19 cm -3。

公开(公告)号：US20120056203A1

公开(公告)日：2012-03-08

申请号：US13320250

申请日：2010-04-27

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Taro Nishiguchi ,  Makoto Sasaki ,  Yasuo Namikawa ,  Shinsuke Fujiwara

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Taro Nishiguchi ,  Makoto Sasaki ,  Yasuo Namikawa ,  Shinsuke Fujiwara

IPC分类号： H01L29/12

CPC分类号： H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/808

摘要： A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.

摘要翻译： 作为允许降低制造成本的半导体器件的JFET包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在所述有源层上的源电极; 以及形成在有源层上并与源电极分离的漏电极。 碳化硅基板包括：由单晶碳化硅制成的基底层和由单晶碳化硅制成并设置在基底层上的SiC层。 SiC层的缺陷密度小于基底层的缺陷密度。

公开(公告)号：US20120056201A1

公开(公告)日：2012-03-08

申请号：US13320243

申请日：2010-04-27

申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Taro Nishiguchi ,  Makoto Sasaki ,  Shinsuke Fujiwara ,  Yasuo Namikawa

发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga ,  Taro Nishiguchi ,  Makoto Sasaki ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC分类号： H01L29/739

CPC分类号： H01L29/7802 ,  C30B23/00 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7395

摘要： An IGBT, which is a vertical type IGBT allowing for reduced on-resistance while restraining defects from being produced, includes: a silicon carbide substrate, a drift layer, a well region, an n+ region, an emitter contact electrode, a gate oxide film, a gate electrode, and a collector electrode. The silicon carbide substrate includes: a base layer made of silicon carbide and having p type conductivity; and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The base layer has a p type impurity concentration exceeding 1×1018 cm−3.

摘要翻译： IGBT是一种允许在抑制缺陷产生的同时降低导通电阻的垂直型IGBT，包括：碳化硅衬底，漂移层，阱区，n +区，发射极接触电极，栅极氧化膜 ，栅电极和集电极。 碳化硅基板包括：由碳化硅制成并具有p型导电性的基底层; 以及由单晶碳化硅制成并设置在基底层上的SiC层。 基极层的p型杂质浓度超过1×1018cm-3。

公开(公告)号：US20120015499A1

公开(公告)日：2012-01-19

申请号：US13256328

申请日：2010-09-28

申请人： Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

发明人： Makoto Sasaki ,  Shin Harada ,  Taro Nishiguchi ,  Kyoko Okita ,  Yasuo Namikawa

IPC分类号： H01L21/04

CPC分类号： H01L21/02667 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/02656 ,  H01L21/047 ,  H01L21/0475 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7802

摘要： A combined substrate is prepared which has a supporting portion and first and second silicon carbide substrates. Between the first and second silicon carbide substrates, a gap having an opening exists. A closing layer for the gap is formed over the opening. The closing layer at least includes a silicon layer. In order to form a cover made of silicon carbide and closing the gap over the opening, the silicon layer is carbonized. By depositing sublimates from the first and second side surfaces of the first and second silicon carbide substrates onto the cover, a connecting portion is formed to close the opening. The cover is removed.

摘要翻译： 制备具有支撑部分和第一和第二碳化硅衬底的组合衬底。 在第一和第二碳化硅衬底之间，存在具有开口的间隙。 在开口上形成用于间隙的闭合层。 封闭层至少包括硅层。 为了形成由碳化硅制成的盖子并且封闭开口上的间隙，硅层被碳化。 通过将第一和第二碳化硅衬底的第一和第二侧表面的升华物沉积到盖上，形成连接部分以封闭开口。 盖子被移除。

公开(公告)号：US20110278595A1

公开(公告)日：2011-11-17

申请号：US13104275

申请日：2011-05-10

申请人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

发明人： Taro Nishiguchi ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Yasuo Namikawa

IPC分类号： H01L29/24 ,  C30B23/02 ,  H01L21/20 ,  B32B13/04

CPC分类号： H01L29/7802 ,  B32B9/00 ,  B32B13/04 ,  B32B2307/202 ,  B32B2307/732 ,  B32B2457/14 ,  C30B29/36 ,  C30B33/06 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02631 ,  H01L21/046 ,  H01L21/049 ,  H01L21/2007 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068

摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing said SiC substrate on and in contact with a main surface of said base substrate; and connecting said base substrate and said SiC substrate to each other by heating said stacked substrate in a container to fall within a range of temperature equal to or greater than a sublimation temperature of silicon carbide constituting said base substrate. In the step of connecting said base substrate and said SiC substrate, a silicon carbide body made of silicon carbide and different from said base substrate and said SiC substrate is disposed in said container.

摘要翻译： 制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 通过将所述SiC衬底放置在所述基底衬底的主表面上并与之接触来制造堆叠衬底; 以及通过在容器中加热所述堆叠的基板而将所述基底基板和所述SiC基板彼此连接，以落入构成所述基底基板的碳化硅的升华温度以上的温度范围内。 在连接所述基底衬底和所述SiC衬底的步骤中，将由碳化硅制成并且与所述基底衬底和所述SiC衬底不同的碳化硅体设置在所述容器中。

公开(公告)号：US20110175107A1

公开(公告)日：2011-07-21

申请号：US13005714

申请日：2011-01-13

申请人： Taro NISHIGUCHI ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

发明人： Taro NISHIGUCHI ,  Makoto Sasaki ,  Shin Harada ,  Kyoko Okita ,  Hiroki Inoue ,  Shinsuke Fujiwara ,  Yasuo Namikawa

IPC分类号： H01L29/16

CPC分类号： H01L21/02378 ,  H01L21/02002 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/30625 ,  H01L29/1608

摘要： A base portion is made of silicon carbide and has a main surface. At least one silicon carbide layer is provided on the main surface of the base portion in a manner exposing a region of the main surface along an outer edge of the main surface. At least one protection layer is provided on this region of the main surface of the base portion along the outer edge of the main surface. Thus, a silicon carbide substrate can be polished with high in-plane uniformity.

摘要翻译： 基部由碳化硅制成并具有主表面。 至少一个碳化硅层以沿着主表面的外边缘露出主表面的区域的方式设置在基部的主表面上。 沿着主表面的外缘在基部的主表面的该区域上设置至少一个保护层。 因此，可以以高的面内均匀性抛光碳化硅衬底。