公开(公告)号：US20120246390A1

公开(公告)日：2012-09-27

申请号：US13345818

申请日：2012-01-09

申请人： Tatsunori Kanai ,  Tetsuro Kimura ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satohi Shirai ,  Akihiro Shibata

发明人： Tatsunori Kanai ,  Tetsuro Kimura ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Masaya Tarui ,  Satohi Shirai ,  Akihiro Shibata

IPC分类号： G06F12/02

CPC分类号： G06F1/1635 ,  G06F1/263 ,  G06F1/305

摘要： According to one embodiment, an information processing apparatus includes an auxiliary storage unit, a non-volatile main storage unit, a secondary cell, a first writing unit, and a second writing unit. The non-volatile main storage unit includes a cache area to temporarily store therein data that is to be stored in the auxiliary storage unit. The first writing unit writes the data into the cache area. The second writing unit writes the data written in the cache area into the auxiliary storage unit when an amount of power in the secondary cell is greater than a predetermined first threshold.

摘要翻译： 根据一个实施例，信息处理设备包括辅助存储单元，非易失性主存储单元，辅助单元，第一写入单元和第二写入单元。 非易失性主存储单元包括用于临时存储要存储在辅助存储单元中的数据的高速缓存区域。 第一个写入单元将数据写入高速缓存区域。 当二次电池中的电力量大于预定的第一阈值时，第二写入单元将写入高速缓存区域中的数据写入辅助存储单元。

公开(公告)号：US08832335B2

公开(公告)日：2014-09-09

申请号：US13334235

申请日：2011-12-22

申请人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

发明人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F1/32 ,  G06F9/48

CPC分类号： G06F1/3243 ,  G06F9/4812 ,  Y02D10/152 ,  Y02D10/24

摘要： According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

摘要翻译： 根据实施例，控制装置包括：接收单元，被配置为接收请求由执行一个或多个处理的处理装置执行的中断处理的中断请求; 存储单元，被配置为在其中存储中断请求; 确定单元，被配置为确定所述处理装置的状态; 发送单元，被配置为将所述中断请求发送到所述处理装置; 以及控制单元，被配置为当所述处理设备被所述确定单元确定为处于处理设备未执行所述处理的空闲状态时，将所述接收单元接收到的所述中断请求存储在所述存储单元中，并且预定条件是 并且当满足预定条件时，控制发送单元将存储在存储单元中的中断请求发送到处理装置。

公开(公告)号：US20120246356A1

公开(公告)日：2012-09-27

申请号：US13334235

申请日：2011-12-22

申请人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

发明人： Akihiro Shibata ,  Koichi Fujisaki ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Satoshi Shirai ,  Masaya Tarui ,  Hiroyoshi Haruki

IPC分类号： G06F13/24

CPC分类号： G06F1/3243 ,  G06F9/4812 ,  Y02D10/152 ,  Y02D10/24

摘要： According to an embodiment, a control device includes a receiving unit configured to receive an interrupt request requesting an interrupt process to be executed by a processing device that executes one or more processes; a storage unit configured to store therein the interrupt request; a determining unit configured to determine a state of the processing device; a sending unit configured to send the interrupt request to the processing device; and a control unit configured to store the interrupt request received by the receiving unit in the storage unit when the processing device is determined by the determining unit to be in an idle state in which the processing device is not executing the processes and a predetermined condition is not satisfied, and to control the sending unit to send the interrupt request stored in the storage unit to the processing device when the predetermined condition is satisfied.

摘要翻译： 根据实施例，控制装置包括：接收单元，被配置为接收请求由执行一个或多个处理的处理装置执行的中断处理的中断请求; 存储单元，被配置为在其中存储中断请求; 确定单元，被配置为确定所述处理装置的状态; 发送单元，被配置为将所述中断请求发送到所述处理装置; 以及控制单元，被配置为当所述处理设备被所述确定单元确定为处于处理设备未执行所述处理的空闲状态时，将所述接收单元接收到的所述中断请求存储在所述存储单元中，并且预定条件是 并且当满足预定条件时，控制发送单元将存储在存储单元中的中断请求发送到处理装置。

公开(公告)号：US20120246501A1

公开(公告)日：2012-09-27

申请号：US13345824

申请日：2012-01-09

申请人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Satoshi Shirai ,  Masaya Tarui ,  Akihiro Shibata ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

发明人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Satoshi Shirai ,  Masaya Tarui ,  Akihiro Shibata ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

IPC分类号： G06F1/32

CPC分类号： G06F9/4893 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

摘要： According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.

摘要翻译： 根据一个实施例，控制器包括状态检测单元，计算单元和确定单元。 状态检测单元检测空闲状态，其中表示不能在能够执行一个或多个处理的处理设备上执行的处理。 当状态检测单元检测到空闲状态时，计算单元计算恢复时间，其指示直到下一个处理开始的时间长度。 确定单元基于由计算单元计算的恢复时间来确定处理装置的操作模式。

公开(公告)号：US09207743B2

公开(公告)日：2015-12-08

申请号：US13724106

申请日：2012-12-21

申请人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Junichi Segawa ,  Satoshi Shirai ,  Yusuke Shirota ,  Akihiro Shibata ,  Masaya Tarui ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

发明人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Junichi Segawa ,  Satoshi Shirai ,  Yusuke Shirota ,  Akihiro Shibata ,  Masaya Tarui ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

IPC分类号： G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3234 ,  G06F1/263 ,  G06F1/3212 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/174 ,  Y02D50/20

摘要： According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.

摘要翻译： 根据实施例，控制装置包括计算器和设定单元。 计算器被配置为计算系统处理时间，其指示系统之后执行的处理所需的时间，该系统包括多个元件，每个元件被单独控制的功率从休眠状态恢复，其中提供的元件的数量 功率被限制为预定数量，并且停止系统的操作。 设置单元被配置为当发生指示用于恢复系统从休眠状态的因素的恢复因子时，根据由计算器计算的系统处理时间来设置指示系统的操作状态的模式。

公开(公告)号：US08868952B2

公开(公告)日：2014-10-21

申请号：US13345824

申请日：2012-01-09

申请人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Satoshi Shirai ,  Masaya Tarui ,  Akihiro Shibata ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

发明人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Satoshi Shirai ,  Masaya Tarui ,  Akihiro Shibata ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

IPC分类号： G06F1/32 ,  G06F9/48

CPC分类号： G06F9/4893 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

摘要： According to one embodiment, a controller includes a state detecting unit, a calculating unit, and a determining unit. The state detecting unit detects an idle state in which indicates there are no process that can execute on a processing device capable of performing one or more processes. The calculating unit calculates a resuming time, which indicates a time length until the next process starts, when the state detecting unit detects the idle state. The determining unit determines an operation mode of the processing device on the basis of the resuming time calculated by the calculating unit.

摘要翻译： 根据一个实施例，控制器包括状态检测单元，计算单元和确定单元。 状态检测单元检测空闲状态，其中表示不能在能够执行一个或多个处理的处理设备上执行的处理。 当状态检测单元检测到空闲状态时，计算单元计算恢复时间，其指示直到下一个处理开始的时间长度。 确定单元基于由计算单元计算的恢复时间来确定处理装置的操作模式。

公开(公告)号：US20130191670A1

公开(公告)日：2013-07-25

申请号：US13724106

申请日：2012-12-21

申请人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Junichi Segawa ,  Satoshi Shirai ,  Yusuke Shirota ,  Akihiro Shibata ,  Masaya Tarui ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

发明人： Hiroyoshi Haruki ,  Koichi Fujisaki ,  Junichi Segawa ,  Satoshi Shirai ,  Yusuke Shirota ,  Akihiro Shibata ,  Masaya Tarui ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/263 ,  G06F1/3212 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D10/174 ,  Y02D50/20

摘要： According to an embodiment, a control device includes a calculator and a setting unit. The calculator is configured to calculate a system processing time indicating a time required for processing executed after a system, the system including a plurality of elements, power to each element being individually controlled, resumes from a sleep state in which the number of elements supplied with power is limited to a predetermined number and an operation of the system is stopped. The setting unit is configured to set a mode indicating an operation state of the system according to the system processing time calculated by the calculator when a resume factor indicating a factor for resuming the system from the sleep state occurs.

摘要翻译： 根据实施例，控制装置包括计算器和设定单元。 计算器被配置为计算系统处理时间，其指示系统之后执行的处理所需的时间，该系统包括多个元件，每个元件被单独控制的功率从休眠状态恢复，其中提供的元件的数量 功率被限制为预定数量，并且停止系统的操作。 设置单元被配置为当发生指示用于恢复系统从休眠状态的因素的恢复因子时，根据由计算器计算的系统处理时间来设置指示系统的操作状态的模式。

公开(公告)号：US20130080813A1

公开(公告)日：2013-03-28

申请号：US13556354

申请日：2012-07-24

申请人： Masaya Tarui ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Tetsuro Kimura ,  Junichi Segawa ,  Yusuke Shirota ,  Satoshi Shirai ,  Akihiro Shibata

发明人： Masaya Tarui ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Tetsuro Kimura ,  Junichi Segawa ,  Yusuke Shirota ,  Satoshi Shirai ,  Akihiro Shibata

IPC分类号： G06F1/32

CPC分类号： G06F12/0893 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

公开(公告)号：US09110667B2

公开(公告)日：2015-08-18

申请号：US13546246

申请日：2012-07-11

申请人： Yusuke Shirota ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Junichi Segawa ,  Masaya Tarui ,  Satoshi Shirai ,  Hiroyoshi Haruki ,  Akihiro Shibata

发明人： Yusuke Shirota ,  Tetsuro Kimura ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Koichi Fujisaki ,  Junichi Segawa ,  Masaya Tarui ,  Satoshi Shirai ,  Hiroyoshi Haruki ,  Akihiro Shibata

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F12/0862 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： According to an embodiment, a control system includes a processing device; a main storage device to store the data; a cache memory to store part of the data stored; a prefetch unit to predict data highly likely to be accessed and execute prefetch, reading out data in advance onto the cache memory; and a power supply unit. The system further includes: a detecting unit to detect whether the processing device is in an idle state; a determining unit that determines whether to stop the supply of power to the cache memory in accordance with the state of the prefetch when determined as idle state; and a power supply control unit that controls the power supply unit so as to stop the supply of power, or controls the power supply unit so as to continue the supply of power.

摘要翻译： 根据实施例，控制系统包括处理装置; 用于存储数据的主存储装置; 用于存储存储的部分数据的高速缓冲存储器; 用于预测非常可能被访问并执行预取的数据的预取单元，预先将数据读出到高速缓冲存储器上; 和电源单元。 该系统还包括：检测单元，用于检测处理设备是否处于空闲状态; 确定单元，当确定为空闲状态时，根据预取的状态确定是否停止向高速缓冲存储器供电; 以及电源控制单元，其控制电源单元以停止电力供应，或者控制电源单元以继续供电。

公开(公告)号：US09043631B2

公开(公告)日：2015-05-26

申请号：US13556354

申请日：2012-07-24

申请人： Masaya Tarui ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Tetsuro Kimura ,  Junichi Segawa ,  Yusuke Shirota ,  Satoshi Shirai ,  Akihiro Shibata

发明人： Masaya Tarui ,  Koichi Fujisaki ,  Hiroyoshi Haruki ,  Tatsunori Kanai ,  Haruhiko Toyama ,  Tetsuro Kimura ,  Junichi Segawa ,  Yusuke Shirota ,  Satoshi Shirai ,  Akihiro Shibata

IPC分类号： G06F1/32

CPC分类号： G06F12/0893 ,  G06F1/3275 ,  G06F1/3287 ,  G06F12/0804 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

摘要翻译： 根据实施例，控制系统包括检测器，估计单元，确定单元和控制器。 检测器检测到空闲状态。 估计单元估计空闲时段。 当检测到空闲状态时，确定单元确定是否执行需要写回到主存储装置的数据的回写的第一功耗以及停止向高速缓冲存储器供电的功率大于第二功率 在不执行数据回写时的消耗，并且在空闲期间继续供电。 当确定第一功率消耗被确定为小于第二功率消耗时，控制器停止向高速缓冲存储器供电，并且当确定第一功耗大于第二功耗时继续供电。