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    Radar hardware accelerator
    2.
    发明授权
    Radar hardware accelerator 有权

    公开(公告)号：US11579242B2

    公开(公告)日：2023-02-14

    申请号：US16442152

    申请日：2019-06-14

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

    IPC分类号： G01S7/02 ,  H04B15/02 ,  H04L27/10 ,  G01S7/35 ,  G01S13/34 ,  G01S13/58 ,  G01S13/42 ,  G01S13/931

    摘要： A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

    Two-dimensional FFT computation
    3.
    发明授权
    Two-dimensional FFT computation 有权

    公开(公告)号：US11221397B2

    公开(公告)日：2022-01-11

    申请号：US16376515

    申请日：2019-04-05

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Pankaj Gupta ,  Karthik Ramasubramanian

    IPC分类号： G01S7/35 ,  G06F17/14 ,  H04L27/26 ,  G06F17/16

    摘要： A system includes a hardware accelerator configured to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log2 M×N pipeline stages including an initial group of log2 M stages and a final group of log2 N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

    Loopback techniques for synchronization of oscillator signal in radar
    4.
    发明授权
    Loopback techniques for synchronization of oscillator signal in radar 有权

    公开(公告)号：US11035928B2

    公开(公告)日：2021-06-15

    申请号：US15642880

    申请日：2017-07-06

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Karthik Subburaj ,  Brian Ginsburg ,  Karthik Ramasubramanian

    IPC分类号： G01S7/03 ,  G01S7/40 ,  G01S13/87 ,  H04L7/04 ,  G01S13/931

    摘要： The disclosure provides a radar apparatus for estimating a position and a velocity of a plurality of obstacles. The radar apparatus includes a slave radar chip. A master radar chip is coupled to the slave radar chip. The master radar chip includes a local oscillator that generates a transmit signal. The slave radar chip receives the transmit signal on a first path and sends the transmit signal back to the master radar chip on a second path. A delay detect circuit is coupled to the local oscillator and receives the transmit signal from the slave radar chip on the second path and the transmit signal from the local oscillator. The delay detect circuit estimates a routing delay from the transmit signal received from the slave radar chip on the second path and from the transmit signal received from the local oscillator.

    NOISE MITIGATION IN RADAR SYSTEMS
    5.
    发明申请
    NOISE MITIGATION IN RADAR SYSTEMS 有权

    公开(公告)号：US20210011118A1

    公开(公告)日：2021-01-14

    申请号：US17020931

    申请日：2020-09-15

    申请人： Texas Instruments Incorporated

    发明人： Karthik Subburaj ,  Karthik Ramasubramanian ,  Sriram Murali ,  Sreekiran Samala ,  Krishnanshu Dandu

    IPC分类号： G01S7/292 ,  G01S13/88 ,  G01S13/00 ,  G01S7/35 ,  G01S13/34 ,  G01S7/03 ,  G01S7/02 ,  G01S7/41

    摘要： A noise-mitigated continuous-wave frequency-modulated radar includes, for example, a transmitter for generating a radar signal, a receiver for receiving a reflected radar signal and comprising a mixer for generating a baseband signal in response to the received radar signal and in response to a local oscillator (LO) signal, and a signal shifter coupled to at least one of the transmitter, LO input of the mixer in the receiver and the baseband signal generated by the mixer. The impact of amplitude noise or phase noise associated with interferers, namely, for example, strong reflections from nearby objects, and electromagnetic coupling from transmit antenna to receive antenna, on the detection of other surrounding objects is reduced by configuring the signal shifter in response to an interferer frequency and phase offset.

    Radar hardware accelerator
    7.
    发明授权
    Radar hardware accelerator 有权

    公开(公告)号：US10330773B2

    公开(公告)日：2019-06-25

    申请号：US15184715

    申请日：2016-06-16

    申请人： Texas Instruments Incorporated

    发明人： Sandeep Rao ,  Karthik Ramasubramanian ,  Indu Prathapan ,  Raghu Ganesan ,  Pankaj Gupta

    IPC分类号： G01S7/02 ,  G01S13/34 ,  H04B15/02 ,  H04L27/10 ,  G01S7/35

    摘要： A radar hardware accelerator (HWA) includes a fast Fourier transform (FFT) engine including a pre-processing block for providing interference mitigation and/or multiplying a radar data sample stream received from ADC buffers within a split accelerator local memory that also includes output buffers by a pre-programmed complex scalar or a specified sample from an internal look-up table (LUT) to generate pre-processed samples. A windowing plus FFT block (windowed FFT block) is for multiply the pre-processed samples by a window vector and then processing by an FFT block for performing a FFT to generate Fourier transformed samples. A post-processing block is for computing a magnitude of the Fourier transformed samples and performing a data compression operation for generating post-processed radar data. The pre-processing block, windowed FFT block and post-processing block are connected in one streaming series data path.

    Synchronization in FMCW Radar Systems
    9.
    发明申请
    Synchronization in FMCW Radar Systems 审中-公开

    公开(公告)号：US20170299693A1

    公开(公告)日：2017-10-19

    申请号：US15635659

    申请日：2017-06-28

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Karthik Ramasubramanian ,  Karthik Subburaj ,  Sachin Bhardwaj

    IPC分类号： G01S7/35 ,  G01S13/58

    CPC分类号： G01S7/35 ,  G01S13/343 ,  G01S13/584 ,  G01S13/726 ,  G01S13/931 ,  G01S2013/0245

    摘要： The disclosure provides a radar apparatus for estimating a position and a velocity of the plurality of obstacles. The radar apparatus includes a local oscillator that generates a first signal. A first transmit unit receives the first signal from the local oscillator and generates a first transmit signal. A frequency shifter receives the first signal from the local oscillator and generates a second signal. A second transmit unit receives the second signal and generates a second transmit signal. The frequency shifter provides a frequency offset to the first signal based on a routing delay mismatch to generate the second signal such that the first transmit signal is phase coherent with the second transmit signal.