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    High Linearity Phase Interpolator
    1.
    发明申请
    High Linearity Phase Interpolator 有权

    公开(公告)号：US20210044300A1

    公开(公告)日：2021-02-11

    申请号：US17080879

    申请日：2020-10-27

    Applicant: Texas Instruments Incorporated

    Inventor： Baher Haroun ,  Wenting Zhou ,  Kai Yiu Tam ,  Reza Hoshyar ,  Ali Kiaei

    IPC: H03L7/16 ,  H03K23/00

    Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

    High linearity phase interpolator
    4.
    发明授权
    High linearity phase interpolator 有权

    公开(公告)号：US10855294B2

    公开(公告)日：2020-12-01

    申请号：US15346524

    申请日：2016-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Baher Haroun ,  Wenting Zhou ,  Kai Yiu Tam ,  Reza Hoshyar ,  Ali Kiaei

    IPC: H03L7/16 ,  H03K23/00

    Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION
    5.
    发明申请
    FRACTIONAL FREQUENCY CLOCK DIVIDER WITH DIRECT DIVISION 审中-公开

    公开(公告)号：US20180097523A1

    公开(公告)日：2018-04-05

    申请号：US15281617

    申请日：2016-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC: H03L7/197

    CPC classification number: H03L7/1976 ,  H03L7/16 ,  H03L7/18 ,  H03L7/1806 ,  H03L7/197

    Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

    Signal-to-noise ratio (SNR) dependent channel tracking for smart utility networks (SUN) orthogonal frequency division multiplexing (OFDM)
    7.
    发明授权
    Signal-to-noise ratio (SNR) dependent channel tracking for smart utility networks (SUN) orthogonal frequency division multiplexing (OFDM) 有权
    用于智能公用事业网络（SUN）的信噪比（SNR）信道跟踪正交频分复用（OFDM）

    公开(公告)号：US08964916B2

    公开(公告)日：2015-02-24

    申请号：US14145431

    申请日：2013-12-31

    Applicant: Texas Instruments Incorporated

    Inventor： Reza Hoshyar ,  Anuj Batra ,  Timothy Mark Schmidl

    IPC: H04B1/10 ,  H04L27/26 ,  H04B17/00

    CPC classification number: H04L27/2647 ,  H04B17/336

    Abstract: An orthogonal frequency-division multiplexed (OFDM)-based receiver for channel tracking with signal-to-noise ratio dependent parameters that includes a memory; and a signal processor, coupled to the memory. The signal processor to estimate a signal-to-noise ratio (SNR) for a received packet of OFDM symbols and determine an SNR region in which the SNR estimate falls, wherein the signal processor implements a different set of finite impulse response (FIR) filter coefficients for each SNR region.

    Abstract translation: 一种用于信道跟踪的基于正交频分复用（OFDM）的接收机，其具有包括存储器的信噪比相关参数; 以及耦合到存储器的信号处理器。 信号处理器，用于估计接收到的OFDM符号分组的信噪比（SNR），并确定SNR估计下降的SNR区域，其中信号处理器实现不同的一组有限脉冲响应（FIR）滤波器 每个SNR区域的系数。

    Fractional frequency clock divider with direct division
    8.
    发明授权
    Fractional frequency clock divider with direct division 有权

    公开(公告)号：US10153777B2

    公开(公告)日：2018-12-11

    申请号：US15281617

    申请日：2016-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Reza Hoshyar ,  Wenting Zhou ,  Ali Kiaei ,  Baher Haroun ,  Ahmad Bahai

    IPC: H03L7/00 ,  H03L7/197 ,  H03L7/16 ,  H03L7/18

    Abstract: Disclosed examples include fractional frequency divider circuits, including a counter to provide phase shifted pulse output signals in response to counting of an adjustable integer number NK cycles of an input clock signal, an output circuit to provide an output clock signal having a first edge between first edges of the pulse output signals, as well as a delta-sigma modulator (DSM), clocked by the second pulse output signal to receive a first predetermined value and to provide a DSM output value, and a phase accumulator to receive a step input value representing a sum of the DSM output value and a second predetermined value. The phase accumulator provides a divisor input signal to the counter, and provides a phase adjustment value to the output circuit to control the position of the first edge of the output clock signal between the first edges of the pulse output signals.

    High Linearity Phase Interpolator
    10.
    发明申请
    High Linearity Phase Interpolator 审中-公开

    公开(公告)号：US20180131378A1

    公开(公告)日：2018-05-10

    申请号：US15346524

    申请日：2016-11-08

    Applicant: Texas Instruments Incorporated

    Inventor： Baher Haroun ,  Wenting Zhou ,  Kai Yiu Tam ,  Reza Hoshyar ,  Ali Kiaei

    IPC: H03L7/081 ,  H03L7/197

    CPC classification number: H03L7/16 ,  H03K23/00

    Abstract: A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

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