-
公开(公告)号：US08566524B2
公开(公告)日：2013-10-22
申请号：US12550844
申请日：2009-08-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/30087 , G06F9/466
摘要： A computer program product for use by a transaction program for managing memory access to a shared memory location for transaction data of a first thread, the shared memory location being accessible by the first thread and a second thread. A string of instructions to complete a transaction of the first thread are executed, beginning with one instruction of the string of instructions. It is determined whether the one instruction is part of an active atomic instruction group (AIG) of instructions associated with the transaction of the first thread. A cache structure and a transaction table which together provide for entries in an active mode for the AIG are located if the one instruction is part of an active AIG. The next instruction is executed under a normal execution mode in response to determining that the one instruction is not part of an active AIG.
摘要翻译： 一种用于由交易程序用于管理对第一线程的交易数据的共享存储器位置的存储器访问的计算机程序产品，所述共享存储器位置可由所述第一线程和第二线程访问。 执行一串完成第一个线程的事务的指令，从指令串的一个指令开始。 确定一个指令是否是与第一线程的事务相关联的指令的活动原子指令组（AIG）的一部分。 如果一个指令是活动的AIG的一部分，则一个缓存结构和一个交易表一起提供用于AIG的活动模式的条目。 响应于确定一个指令不是活动AIG的一部分，在正常执行模式下执行下一个指令。
-
2.发明申请公开(公告)号：US20110271079A1
公开(公告)日：2011-11-03
申请号：US13182181
申请日：2011-07-13
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
-
公开(公告)号：US08095750B2
公开(公告)日：2012-01-10
申请号：US11928594
申请日：2007-10-30
CPC分类号： G06F9/467 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0864
摘要： A computing system processes memory transactions for parallel processing of multiple threads of execution by support of which an application need not be aware. The computing system transactional memory support provides a Transaction Table in memory and performs fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. A transaction program employs a plurality of Set Associative Transaction Tables, one for each microprocessor, and Load and Store Summary Tables in memory for fast processing of common conflict.
摘要翻译： 计算系统通过支持哪个应用程序不需要知道来处理用于并行处理多个执行线程的存储器事务。 计算系统事务内存支持在内存中提供一个事务表，并执行快速检测多个事务之间的潜在冲突。 特殊说明可能标记交易的边界，并确定适用于交易的记忆位置。 “私有交易”（PTRAN）标签使得能够快速检测与在所述计算系统的另一个线程上并发执行的其他事务的潜在冲突。 标记表示（或不）内存中的数据条目是系统中当前处于活动状态的未提交事务的推测性存储器状态的一部分。 事务程序使用多个集合关联事务表，每个微处理器一个，存储器中的加载和存储摘要表用于快速处理共同冲突。
-
公开(公告)号：US6047367A
公开(公告)日：2000-04-04
申请号：US9828
申请日：1998-01-20
CPC分类号： G06F9/3885 , G06F9/30116 , G06F9/3012 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： A system and method for improving microprocessor computer system out of order support via register management with synchronization of multiple pipelines and providing for processing a sequential stream of instructions in a computer system having a first and a second processing element, each of the processing elements having its own state determined by a setting of its own general purpose and control registers. When at any point in the processing of said sequential stream of instructions by said first processing element it becomes beneficial to have the second processing element begin continued processing of the same sequential instruction stream then the first and second processing elements process the sequential stream of instructions and may be executing the very same instruction but only one of said processing elements is permitted to change the overall architectural state of said computer system which is determined by a combination of the states of said first and second processing elements. The second processor will have more pipeline stages than the first in order processor to feed the first processor and reduce the finite cache penalty and increase performance. The processing and storage of results of the second processor does not change the architectural state of the computer system. Results are stored in its gprs or its personal storage buffer. Resynchronization of states with a coprocessor occurs upon an invalid op, a stall or a computed specific benefit to processing with the coprocessor as a speculative coprocessor.
摘要翻译： 一种用于通过具有多个管线同步的寄存器管理来改进微处理器计算机系统的无序支持的系统和方法，并且在具有第一和第二处理元件的计算机系统中提供处理顺序的指令流，每个处理元件具有其 自己的状态由其自己的通用和控制寄存器的设置决定。 当处理由所述第一处理单元的所述顺序指令流的任何一点时，有利的是使第二处理单元开始对相同的顺序指令流的连续处理，然后第一和第二处理单元处理顺序的指令流， 可以执行相同的指令，但只允许所述处理单元中的一个改变由所述第一和第二处理单元的状态的组合确定的所述计算机系统的整体架构状态。 第二个处理器将具有比第一个处理器更多的流水线阶段来馈送第一个处理器，并减少有限的缓存损坏并提高性能。 第二处理器的结果的处理和存储不改变计算机系统的架构状态。 结果存储在其gprs或其个人存储缓冲区中。 具有协处理器的状态的重新同步发生在无效操作，停顿或计算的特定利益上，以协处理器作为推测协处理器进行处理。
-
公开(公告)号：US08862786B2
公开(公告)日：2014-10-14
申请号：US12550896
申请日：2009-08-31
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： Program execution with improved power efficiency including a computer program that for performing a method that includes determining a current power state of a processor. Low power state instructions of an application are executed on the processor in response to determining that the current power state of the processor is a low power state. Executing the low power state instructions includes collecting hardware state data, storing the hardware state data, and performing a task. High power state instructions of the application are executed on the processor in response to determining that the current power state of the processor is a high power state. Executing the high power state instructions includes performing the task using the stored hardware state data as an input.
摘要翻译： 具有提高的功率效率的程序执行，包括用于执行包括确定处理器的当前功率状态的方法的计算机程序。 响应于确定处理器的当前功率状态是低功率状态，在处理器上执行应用的低功率状态指令。 执行低功率状态指令包括收集硬件状态数据，存储硬件状态数据和执行任务。 响应于确定处理器的当前功率状态是高功率状态，在处理器上执行应用的高功率状态指令。 执行高功率状态指令包括使用存储的硬件状态数据作为输入来执行任务。
-
6.发明授权Microprocessor with software control over allocation of shared resources among multiple virtual servers 失效具有软件控制的微处理器，可在多个虚拟服务器之间分配共享资源公开(公告)号：US08676976B2
公开(公告)日：2014-03-18
申请号：US12392665
申请日：2009-02-25
IPC分类号： G06F15/16
CPC分类号： G06F9/5011
摘要： A system and computer program product for controlling the allocation of shared resources. The system includes a next request priority module connected to a shared resource and to a plurality of requesters identified by requester identifiers. The next request priority module includes a pending request mechanism that prioritizes pending requests for the shared resource, a logging mechanism logging requester identifiers associated with previous grants to the shared resource, and next request priority logic. The next request priority logic accesses the next pending request to determine if it should be granted priority to the shared resource. The determining is responsive to logged requester identifiers and to the next requester identifier. Priority is granted to the shared resource to the next pending request in response to determining that the next pending request should be granted priority to the shared resource. The next requester identifier is logged in response to the granting.
摘要翻译： 一种用于控制共享资源分配的系统和计算机程序产品。 该系统包括连接到共享资源的下一个请求优先级模块和由请求者标识符标识的多个请求者。 下一个请求优先级模块包括一个待处理的请求机制，用于对共享资源的挂起请求进行优先级排序，记录机制记录请求者与先前对共享资源的授权相关联的标识符以及下一个请求优先级逻辑。 下一个请求优先级逻辑访问下一个待处理请求，以确定是否应该授予共享资源的优先权。 该确定响应于记录的请求者标识符和下一个请求者标识符。 响应于确定下一个未决请求应被授予共享资源的优先级，优先级被授予共享资源到下一个未决请求。 下一个请求者标识符被记录以响应授权。
-
7.发明授权Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory 失效用于通过事务记忆在陷阱之后恢复记忆一致性的方法，装置和制品公开(公告)号：US08032736B2
公开(公告)日：2011-10-04
申请号：US12037888
申请日：2008-02-26
申请人： Alexander Abrashkevich , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, Jr. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
发明人： Alexander Abrashkevich , Dmitri Abrashkevich , Robert J. Blainey , Thomas J. Heller, Jr. , Matthew A. Huras , Sridhar Munireddy , Yogendra K. Srivastava , Mark F. Wilding
CPC分类号： G06F9/467 , G06F11/1474
摘要： Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.
摘要翻译： 本发明的实施例提供一种通过事务存储器在陷阱之后恢复存储器一致性的方法。 事务内存和事务性内存日志用于撤消从事务起始点到陷阱事件点对内存所做的更改。 处理陷阱事件后，回滚更改，程序可以在事务开始时恢复执行。
-
公开(公告)号：US08028290B2
公开(公告)日：2011-09-27
申请号：US11468547
申请日：2006-08-30
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
摘要翻译： 在为多个指令集架构（ISA）需要多重支持的虚拟机环境中提供功率高效灵活的平台的系统中支持多指令集架构。 处理器包括具有不同的本机ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 虚拟机管理程序控制核心的操作，定位核心，并在必要时启用实例化具有指定ISA的虚拟机的请求。 ISA可以由特定的操作系统和/或应用程序要求来指定。
-
公开(公告)号：US09009452B2
公开(公告)日：2015-04-14
申请号：US11928533
申请日：2007-10-30
CPC分类号： G06F9/3885 , G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/1405 , G06F11/141 , G06F11/1474
摘要： A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A ‘private to transaction’ (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. Program millicode provides transactional memory functions including creating and updating transaction tables, committing transactions and controlling the rollback of transactions which fail.
-
10.发明授权公开(公告)号：US08806182B2
公开(公告)日：2014-08-12
申请号：US13182181
申请日：2011-07-13
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.
摘要翻译： 支持多指令集架构的多核处理器为需要多个支持多指令集体系结构（ISAs）的虚拟机环境提供功率高效且灵活的平台。 处理器包括具有不同的本地ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 多个核心可以共享公共的第一级高速缓存并且被互斥地选择用于操作，或者可以提供多个一级缓存，一个与每个核心和根据需要运行的核心相关联，包括同时执行不同的ISA。 虚拟机管理程序控制核心的操作并定位核心，并且如果需要，当接收到具有指定的ISA的虚拟机的实例化请求时，它可以启用它。
-
-
-
-
-
-
-
-
-
搜索结果
25 条记录 (耗时 0.015 秒)
