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公开(公告)号：US08576608B2
公开(公告)日：2013-11-05
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译： 存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器 单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化 特征为第一电阻变化元件。
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公开(公告)号：US20120212994A1
公开(公告)日：2012-08-23
申请号：US13310839
申请日：2011-12-05
申请人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
发明人： Tomohito Tsushima , Makoto Kitagawa , Tsunenori Shiimoto , Chieko Nakashima , Hiroshi Yoshihara , Kentaro Ogata
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5614 , G11C13/0011 , G11C13/004 , G11C2013/0042 , H01L27/101 , H01L45/085 , H01L45/1233 , H01L45/141 , H01L45/146
摘要： A memory apparatus includes: a plurality of memory cells which includes a first resistance change element; and a read-out circuit which determines the size of a resistance value of the first resistance change element by comparing the resistance state of a memory cell selected among the plurality of memory cells to the resistance state of a reference memory cell, wherein the reference memory cell includes a second resistance change element, a resistance value of the second resistance change element with respect to an applied voltage is smaller than that in a high resistance state of the first resistance change element, and the second resistance change element shows the same resistance change characteristic as the first resistance change element.
摘要翻译： 存储装置包括：多个存储单元，包括第一电阻变化元件; 以及读出电路，其通过将从所述多个存储单元中选择的存储单元的电阻状态与参考存储单元的电阻状态进行比较来确定所述第一电阻变化元件的电阻值的大小，其中所述参考存储器 单元包括第二电阻变化元件，第二电阻变化元件相对于施加电压的电阻值小于第一电阻变化元件的高电阻状态的电阻值，第二电阻变化元件显示相同的电阻变化 特征为第一电阻变化元件。
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3.发明申请Control voltage generation circuit and nonvolatile storage device having the same 审中-公开控制电压产生电路和具有该电压产生电路的非易失性存储装置公开(公告)号：US20110222355A1
公开(公告)日：2011-09-15
申请号：US13064009
申请日：2011-03-02
CPC分类号： G11C16/28 , G11C11/1673 , G11C13/0002 , G11C13/004 , G11C2013/0054
摘要： Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage.
摘要翻译： 这里公开了一种控制电压产生电路，包括：参考电压产生电路，用于产生参考电压; 以及电压转换电路，其适于基于所述参考电压产生要提供给连接在位线和读出放大器之间的钳位晶体管的栅极的控制电压，以调整所述位线的电压，其中所述电压转换 电路将作为与参考电压成比例的电压和与钳位晶体管的阈值电压相当的电压的和的电压作为控制电压输出到钳位晶体管的栅极。
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公开(公告)号：US20060067114A1
公开(公告)日：2006-03-30
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US07372718B2
公开(公告)日：2008-05-13
申请号：US11243342
申请日：2005-10-04
申请人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
发明人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
摘要翻译： 存储装置包括存储元件，其具有使得其电阻值由于高于或等于施加的第一阈值信号的电信号而从高状态变为低状态的特性，并且从低状态改变为 作为高于或等于极性与施加的第一阈值信号的极性不同的第二阈值信号的电信号的结果的高状态; 以及电路元件，其与所述存储元件串联连接并用作负载，所述存储元件和所述电路元件形成存储单元，并且所述存储单元被布置成矩阵，其中所述电路元件的电阻值 当存储元件被读取时与存储元件被写入或擦除时的电阻值不同。
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公开(公告)号：US07242606B2
公开(公告)日：2007-07-10
申请号：US11225593
申请日：2005-09-13
申请人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
发明人： Hidenari Hachino , Nobumichi Okazaki , Wataru Otsuka , Tomohito Tsushima , Tsutomu Sagara , Chieko Nakashima , Hironobu Mori , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C13/02 , G11C13/0069 , G11C2213/79
摘要： A storage apparatus includes memory devices each having a storage element with a characteristic that the application of an electric signal not lower than a first threshold signal allows the storage element to shift from a high resistance value state to a low resistance value state, and that the application of an electric signal not lower than a second threshold signal, which has a polarity different from that of the first threshold signal, allows the storage element to shift form a low resistance value state to a high resistance value state, and a circuit element connected to the storage element in series to be a load; wherein the memory devices are arranged in a matrix and one terminal of each of the memory devices is connected to a common line; and wherein an intermediate potential between a power supply potential and a ground potential is applied to the common line.
摘要翻译： 一种存储装置，具有各自具有存储元件的存储器件，该存储元件具有不低于第一阈值信号的电信号的施加使得存储元件从高电阻值状态向低电阻值状态移动的特征， 施加不低于第一阈值信号极性的第二阈值信号的电信号允许存储元件从低电阻值状态移位到高电阻值状态，并且连接的电路元件 将串联的存储元件作为负载; 其中所述存储器件被布置在矩阵中，并且每个所述存储器件的一个端子连接到公共线; 并且其中电源电位和接地电位之间的中间电位被施加到公共线。
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公开(公告)号：US20060109316A1
公开(公告)日：2006-05-25
申请号：US11243342
申请日：2005-10-04
申请人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
发明人： Hajime Nagao , Hidenari Hachino , Tsutomu Sagara , Hironobu Mori , Nobumichi Okazaki , Wataru Ootsuka , Tomohito Tsushima , Chieko Nakashima
IPC分类号： B41J2/05
CPC分类号： G11C13/00 , G11C13/0069 , G11C2013/0078 , G11C2013/009 , G11C2213/79
摘要： A storage device includes a storage element having characteristics such that the resistance value thereof changes from a high state to a low state as a result of an electrical signal higher than or equal to a first threshold signal being applied and changes from a low state to a high state as a result of an electrical signal higher than or equal to a second threshold signal whose polarity differs from that of the first threshold signal being applied; and a circuit element that is connected in series to the storage element and that serves as a load, the storage element and the circuit element forming a memory cell, and the memory cells being arranged in a matrix, wherein the resistance value of the circuit element when the storage element is read differs from the resistance value when the storage element is written or erased.
摘要翻译： 存储装置包括存储元件，其具有使得其电阻值由于高于或等于施加的第一阈值信号的电信号而从高状态变为低状态的特性，并且从低状态改变为 作为高于或等于极性与施加的第一阈值信号的极性不同的第二阈值信号的电信号的结果的高状态; 以及电路元件，其与所述存储元件串联连接并用作负载，所述存储元件和所述电路元件形成存储单元，并且所述存储单元被布置成矩阵，其中所述电路元件的电阻值 当存储元件被读取时与存储元件被写入或擦除时的电阻值不同。
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公开(公告)号：US20070070682A1
公开(公告)日：2007-03-29
申请号：US11530716
申请日：2006-09-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R≧V/I.
摘要翻译： 存储装置包括具有存储元件的存储单元，存储元件具有通过提供等于或高于第一阈值电压的电压而从高电阻值状态变为低电阻值状态的特性，以及改变 通过提供等于或高于极性与第一阈值电压不同的第二阈值电压的电压，从低电阻值的状态到高电阻值的状态，以及与存储器串联连接的电路元件 元件，其中令R为写入后存储元件的电阻值，V为第二阈值电压，I为在擦除时能够通过存储元件的电流R> = V / I。
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公开(公告)号：US07209379B2
公开(公告)日：2007-04-24
申请号：US11224856
申请日：2005-09-13
申请人： Hironobu Mori , Hidenari Hachino , Chieko Nakashima , Tsutomu Sagara , Nobumichi Okazaki , Hajime Nagao
发明人： Hironobu Mori , Hidenari Hachino , Chieko Nakashima , Tsutomu Sagara , Nobumichi Okazaki , Hajime Nagao
IPC分类号： G11C11/00
CPC分类号： G11C11/22 , G11C13/0007 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0066 , G11C2213/79
摘要： A storage device is proposed, which includes: a source line arranged along a row direction; a bit line arranged along a column direction; a storage element arranged at an intersection of the source line and the bit line; a writing circuit connected to one terminal of the bit line and applying a predetermined voltage to the bit line; and a voltage adjusting circuit connected to a storage element that is located closest to another terminal of the bit line; wherein the voltage adjusting circuit compares the voltage applied to the storage element located closest to the another terminal of the bit line with a setting voltage to thereby adjust the voltage that the writing circuit applies to the bit line.
摘要翻译： 提出了一种存储装置，其包括：沿着行方向布置的源极线; 沿列方向布置的位线; 存储元件，其布置在所述源极线和所述位线的交叉点处; 写入电路，连接到所述位线的一个端子并向所述位线施加预定电压; 以及电压调整电路，其连接到最靠近所述位线的另一个端子的存储元件; 其中，所述电压调整电路将施加到位于最靠近所述位线的另一端子的存储元件的电压与设定电压进行比较，从而调整所述写入电路对所述位线施加的电压。
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公开(公告)号：US07471543B2
公开(公告)日：2008-12-30
申请号：US11530716
申请日：2006-09-11
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/79
摘要： A storage device includes a memory cell having a storage element having a characteristic of changing from a state of a high resistance value to a state of a low resistance value by being supplied with a voltage equal to or higher than a first threshold voltage, and changing from a state of a low resistance value to a state of a high resistance value by being supplied with a voltage equal to or higher than a second threshold voltage different in polarity from the first threshold voltage, and a circuit element connected in series with the storage element, wherein letting R be a resistance value of the storage element after writing, V be the second threshold voltage, and I be a current that can be passed through the storage element at a time of erasure, R≧V/I.
摘要翻译： 存储装置包括具有存储元件的存储单元，存储元件具有通过提供等于或高于第一阈值电压的电压而从高电阻值状态变为低电阻值状态的特性，以及改变 通过提供等于或高于极性与第一阈值电压不同的第二阈值电压的电压，从低电阻值的状态到高电阻值的状态，以及与存储器串联连接的电路元件 元件，其中令R为写入后存储元件的电阻值，V为第二阈值电压，I为在擦除时能够通过存储元件的电流R> = V / I。
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