公开(公告)号：US6146966A

公开(公告)日：2000-11-14

申请号：US859210

申请日：1997-05-20

申请人： Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

发明人： Toshiyuki Hirota ,  Hirohito Watanabe ,  Fumiki Aiso ,  Shuji Fujiwara ,  Masanobu Zenke

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： In a process of forming hemi-spherical silicon grains on an amorphous silicon film in accordance with the "crystal nucleation" process, in order to form crystal nuclei on a top surface and a side surface of the amorphous silicon film, SiH.sub.4 is irradiated onto the top and side surfaces of the amorphous silicon film at a stabilized temperature which is lower than, by at least 5.degree. C., an annealing temperature for growing the hemi-spherical silicon grains from the crystal nuclei, with the result that it is possible to suppress or retard the growth of the crystals growing into the amorphous silicon film from a boundary between the amorphous silicon film and an interlayer insulator film. Thereafter, the amorphous silicon film having the crystal nuclei thus formed on the surface thereof is annealed at the annealing temperature so that the hemi-spherical silicon grains are formed on the whole surface of the top and side surfaces of the amorphous silicon film.

摘要翻译： 在根据“晶体成核”法在非晶硅膜上形成半球形硅晶粒的过程中，为了在非晶硅膜的顶表面和侧表面上形成晶核，将SiH 4照射到 该非晶硅膜的顶表面和侧表面在稳定的温度下低于至少5℃的用于从晶核生长半球形硅晶粒的退火温度，结果是可以 从非晶硅膜和层间绝缘膜之间的边界抑制或延缓从非晶硅膜生长的晶体的生长。 此后，在其表面上形成具有晶核的非晶硅膜在退火温度下退火，使得半球形硅晶粒形成在非晶硅膜的顶表面和侧表面的整个表面上。

公开(公告)号：US5959326A

公开(公告)日：1999-09-28

申请号：US852530

申请日：1997-05-07

申请人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

发明人： Fumiki Aiso ,  Hirohito Watanabe ,  Toshiyuki Hirota ,  Masanobu Zenke ,  Shuji Fujiwara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/205 ,  H01L21/283 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G4/06

CPC分类号： H01L28/84

摘要： In a capacitor incorporated in a semiconductor device, a capacitor lower plate is formed of a first amorphous silicon film on an interlayer insulator film and a second amorphous silicon film stacked on the first amorphous silicon film. A crystallization preventing film is formed between the first and second amorphous silicon films, or alternatively, the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. A stacked structure formed of the first and second amorphous silicon films is patterned into a capacitor lower plate having a top surface and a side surface, and hemispherical grains are formed on not only the top surface but also the side surface of the patterned stacked structure. In this process, crystalline growth from the interlayer insulator film is prevented by the crystallization preventing film or by the fact that the first amorphous silicon film is formed to have an impurity concentration lower than that of the second amorphous silicon film. Thus, concaves and convexes in the form of hemispherical grains are uniformly formed on not only the top surface but also the side surface of the patterned stacked structure, so that a remarkably increased capacitance can be obtained.

摘要翻译： 在并入半导体装置的电容器中，电容器下板由层叠绝缘膜上的第一非晶硅膜和层叠在第一非晶硅膜上的第二非晶硅膜形成。 在第一和第二非晶硅膜之间形成结晶防止膜，或者，形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度。 由第一和第二非晶硅膜形成的堆叠结构被图案化成具有顶表面和侧表面的电容器底板，并且半球形晶粒不仅形成在图案化堆叠结构的顶表面而且形成在侧表面上。 在该方法中，通过防止结晶化膜或者形成第一非晶硅膜的杂质浓度低于第二非晶硅膜的杂质浓度来防止来自层间绝缘膜的晶体生长。 因此，半球状晶粒形式的凹凸不仅在图案化叠层结构的顶表面，而且均匀地形成，从而可以获得显着增加的电容。

公开(公告)号：US5858852A

公开(公告)日：1999-01-12

申请号：US853744

申请日：1997-05-09

申请人： Fumiki Aiso ,  Toshiyuki Hirota

发明人： Fumiki Aiso ,  Toshiyuki Hirota

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L28/84

摘要： At first, a silicon oxide layer is selectively formed on the surface of a semiconductor substrate. Next, a first amorphous silicon film doped with phosphorous in the concentration of about 1.times.10.sup.20 (atoms/cm.sup.3) and a non-doped second amorphous silicon film are deposited in sequential order. By this, an amorphous silicon layer for lower electrode constituted of the first and second amorphous silicon films is formed. Then, an HSG (unevenness) is formed on the surface of the amorphous silicon layer for lower electrode. Subsequently, the amorphous silicon layer for lower electrode is patterned to form a lower electrode of the stack type capacitive element. Thereafter, a capacitance insulation layer is formed on the upper surface and the side surface of the lower electrode. Then, over the entire surface, an upper electrode is deposited.

摘要翻译： 首先，在半导体衬底的表面上选择性地形成氧化硅层。 接下来，依次沉积掺杂浓度为约1×10 20（原子/ cm 3）的磷和非掺杂的第二非晶硅膜的第一非晶硅膜。 由此，形成由第一和第二非晶硅膜构成的用于下电极的非晶硅层。 然后，在用于下电极的非晶硅层的表面上形成HSG（凹凸）。 随后，将用于下电极的非晶硅层图案化以形成堆叠型电容元件的下电极。 此后，在下电极的上表面和侧表面上形成电容绝缘层。 然后，在整个表面上沉积上电极。

公开(公告)号：US07351654B2

公开(公告)日：2008-04-01

申请号：US11132258

申请日：2005-05-19

申请人： Norishiro Komatsu ,  Fumiki Aiso ,  Toshiyuki Hirota

发明人： Norishiro Komatsu ,  Fumiki Aiso ,  Toshiyuki Hirota

IPC分类号： H01L21/4763

CPC分类号： H01L21/28525 ,  H01L21/76877 ,  H01L21/76888 ,  H01L27/10888

摘要： A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在衬底上形成硅晶核，沉积第一非晶硅，沉积第二非晶硅，并通过使晶核在固体中生长而使第一非晶硅和第二非晶硅结晶 相。

公开(公告)号：US20070238310A1

公开(公告)日：2007-10-11

申请号：US11697082

申请日：2007-04-05

申请人： Yo Matsuda ,  Fumiki Aiso ,  Toshiyuki Hirota

发明人： Yo Matsuda ,  Fumiki Aiso ,  Toshiyuki Hirota

IPC分类号： H01L21/31

CPC分类号： H01L21/0214 ,  H01L21/02063 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/76229 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76837 ,  H01L21/76897

摘要： A semiconductor device manufacturing method includes: a process of forming an isolation trench on the surface of a semiconductor substrate; a process of forming a thermally-oxidized film on the surface of the isolation trench; a process of depositing a silicon oxynitride film on the semiconductor substrate via the thermally-oxidized film; a process of heat-treating the silicon oxynitride film in an oxidizing atmosphere; and a process of etching the top of the thermally-oxidized film and the heat-treated silicon oxynitride film.

摘要翻译： 半导体器件制造方法包括：在半导体衬底的表面上形成隔离沟槽的工艺; 在隔离沟槽的表面上形成热氧化膜的工艺; 通过热氧化膜在半导体衬底上沉积氮氧化硅膜的工艺; 在氧化气氛中对氧氮化硅膜进行热处理的工序; 以及蚀刻热氧化膜的顶部和热处理的氮氧化硅膜的工序。

公开(公告)号：US20050260862A1

公开(公告)日：2005-11-24

申请号：US11132258

申请日：2005-05-19

申请人： Norishiro Komatsu ,  Fumiki Aiso ,  Toshiyuki Hirota

发明人： Norishiro Komatsu ,  Fumiki Aiso ,  Toshiyuki Hirota

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/20 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L21/28525 ,  H01L21/76877 ,  H01L21/76888 ,  H01L27/10888

摘要： A method for producing a semiconductor device includes the steps of forming silicon crystal nuclei on a substrate, depositing first amorphous silicon, depositing second amorphous silicon, and crystallizing the first amorphous silicon and the second amorphous silicon by allowing the crystal nuclei to grow in the solid phase.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在衬底上形成硅晶核，沉积第一非晶硅，沉积第二非晶硅，并通过使晶核在固体中生长而使第一非晶硅和第二非晶硅结晶 相。

公开(公告)号：US06376328B1

公开(公告)日：2002-04-23

申请号：US09584947

申请日：2000-06-01

申请人： Fumiki Aiso ,  Toshiyuki Hirota

发明人： Fumiki Aiso ,  Toshiyuki Hirota

IPC分类号： H01L2120

CPC分类号： H01L28/84 ,  H01L28/91

摘要： A silicon layer containing microcrystal is formed on a semiconductor substrate 10 having an amorphous silicon layer 61a formed on the surface thereof (t1 and t2). Continuously, HSGs (hemispherical grains) are formed, in the same furnace, on the silicon layer 61a using microcrystal on the silicon layer 61a as a nucleus (t2 and t3). Further, a source gas containing impurities is introduced into the furnace to diffuse impurities into the HSGs (t3 and t4), wherein a lower electrode is formed. Also, during the processes from t1 through t4, the partial pressure of water and oxygen in the furnace is set to 1×10−6 Torr or less. Furthermore, during the processes from t1 through t4, the temperature in the furnace is set to 550 through 600° C.

摘要翻译： 在具有形成在其表面上的非晶硅层61a（t1和t2）的半导体衬底10上形成含有微晶体的硅层。 连续地，在相同的炉子中，在作为核的硅层61a上使用微晶的硅层61a（t2和t3）上形成HSG（半球状晶粒）。 此外，将含有杂质的源气体引入炉中以将杂质扩散到HSG（t3和t4）中，其中形成下电极。 此外，在从t1到t4的过程中，炉中的水和氧的分压设定为1×10 -6 Torr或更小。 此外，在t1〜t4的处理中，将炉内的温度设定为550〜600℃

公开(公告)号：US08618603B2

公开(公告)日：2013-12-31

申请号：US13546074

申请日：2012-07-11

申请人： Yoshio Ozawa ,  Fumiki Aiso

发明人： Yoshio Ozawa ,  Fumiki Aiso

IPC分类号： H01L29/66

CPC分类号： H01L27/11578 ,  H01L21/8221 ,  H01L27/11568 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

摘要翻译： 非易失性半导体存储器件包括：半导体部件; 记录膜，设置在所述半导体构件的表面上并能够存储电荷; 以及设置在所述存储膜上的多个控制栅电极，彼此间​​隔开并且沿着与所述表面平行的方向布置。 插入在一个控制栅电极之间的材料和位于与控制栅电极相邻的控制栅电极正下方的部分的平均介电常数低于介于一个控制栅之间的材料的平均介电常数 电极和位于一个控制栅电极正下方的半导体部件的一部分。

公开(公告)号：US07651930B2

公开(公告)日：2010-01-26

申请号：US12146802

申请日：2008-06-26

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US07482235B2

公开(公告)日：2009-01-27

申请号：US11410118

申请日：2006-04-25

申请人： Fumiki Aiso

发明人： Fumiki Aiso

IPC分类号： H01L21/20 ,  C30B25/02

CPC分类号： H01L29/66628 ,  H01L27/10888

摘要： A semiconductor device with an elevated source/drain structure provided in each predetermined position defined by the oxide film and gate wiring on a semiconductor silicon substrate, where an orthographic projection image of a shape of an upper end portion of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is substantially in agreement with a predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate, and at least one of orthographic projection images of cross-sections taken along planes parallel with the semiconductor silicon substrate of the elevated source/drain structure on the semiconductor silicon substrate along the direction normal to the semiconductor silicon substrate is larger than the predetermined shape defined by the corresponding oxide film and gate wiring on the semiconductor silicon substrate.

摘要翻译： 一种具有升高的源/漏结构的半导体器件，其设置在由半导体硅衬底上的氧化物膜和栅极布线限定的每个预定位置上，其中升高的源极/漏极结构的上端部分的形状的正投影图像位于 半导体硅衬底沿着与半导体硅衬底垂直的方向基本上与由半导体硅衬底上相应的氧化物膜和栅极布线限定的预定形状一致，并且至少一个正交投影图像沿着 平行于半导体硅衬底上的升高的源极/漏极结构的半导体硅衬底的平面沿着与半导体硅衬底垂直的方向平行的面大于由半导体硅衬底上相应的氧化物膜和栅极布线限定的预定形状。