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公开(公告)号：US20240324472A1
公开(公告)日：2024-09-26
申请号：US18679437
申请日：2024-05-30
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20230240151A1
公开(公告)日：2023-07-27
申请号：US18122730
申请日：2023-03-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu- Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
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公开(公告)号：US20160181383A1
公开(公告)日：2016-06-23
申请号：US14613343
申请日：2015-02-03
Applicant: United Microelectronics Corp.
Inventor： Shih-Hsien Huang , Che-Wei Chang , Chih-Chieh Yeh , Tzu-I Tsai
IPC: H01L29/417 , H01L29/78 , H01L29/08 , H01L21/285 , H01L21/302 , H01L29/66 , H01L29/45
CPC classification number: H01L29/41791 , H01L21/28518 , H01L21/302 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L29/0847 , H01L29/41758 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess. The epitaxial structure is disposed in the substrate. The recess is formed in the epitaxial structure, where the recess has a cross-section in a direction perpendicular to the substrate, and at least one portion of the recess is gradually expanded from an opening of the recess.
Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括衬底，外延结构和凹部。 外延结构设置在基板中。 凹槽形成在外延结构中，其中凹部在垂直于衬底的方向上具有横截面，并且凹部的至少一部分从凹部的开口逐渐膨胀。
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公开(公告)号：US12232425B2
公开(公告)日：2025-02-18
申请号：US18515273
申请日：2023-11-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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公开(公告)号：US11917923B2
公开(公告)日：2024-02-27
申请号：US17242322
申请日：2021-04-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Ching-Hua Hsu , Si-Han Tsai , Shun-Yu Huang , Chen-Yi Weng , Ju-Chun Fan , Che-Wei Chang , Yi-Yu Lin , Po-Kai Hsu , Jing-Yin Jhang , Ya-Jyuan Hung
Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
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Patent Agency Ranking
公开(公告)号：US20210399209A1
公开(公告)日：2021-12-23
申请号：US17463541
申请日：2021-08-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US20210389394A1
公开(公告)日：2021-12-16
申请号：US16927918
申请日：2020-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US20210066579A1
公开(公告)日：2021-03-04
申请号：US16589083
申请日：2019-09-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US09466678B2
公开(公告)日：2016-10-11
申请号：US14613343
申请日：2015-02-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Hsien Huang , Che-Wei Chang , Chih-Chieh Yeh , Tzu-I Tsai
IPC: H01L21/00 , H01L29/417 , H01L29/66 , H01L29/78 , H01L29/45 , H01L21/285 , H01L21/302 , H01L29/08
CPC classification number: H01L29/41791 , H01L21/28518 , H01L21/302 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L29/0847 , H01L29/41758 , H01L29/458 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
Abstract: The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, an epitaxial structure, and a recess. The epitaxial structure is disposed in the substrate. The recess is formed in the epitaxial structure, where the recess has a cross-section in a direction perpendicular to the substrate, and at least one portion of the recess is gradually expanded from an opening of the recess.
Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括衬底，外延结构和凹部。 外延结构设置在基板中。 凹槽形成在外延结构中，其中凹部在垂直于衬底的方向上具有横截面，并且凹部的至少一部分从凹部的开口逐渐膨胀。
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公开(公告)号：US20250035718A1
公开(公告)日：2025-01-30
申请号：US18915389
申请日：2024-10-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen -Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.
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