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    Dynamic oxide semiconductor random access memory(DOSRAM) having a capacitor electrically connected to the random access memory (SRAM)
    1.
    发明授权
    Dynamic oxide semiconductor random access memory(DOSRAM) having a capacitor electrically connected to the random access memory (SRAM) 有权

    公开(公告)号：US10276578B2

    公开(公告)日：2019-04-30

    申请号：US15632378

    申请日：2017-06-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hsien-Hung Tsai

    IPC: H01L27/108 ,  H01L27/11 ,  H01L29/24

    Abstract: The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.

    MEMORY SYSTEM CAPABLE OF GENERATING NOTIFICATION SIGNALS
    2.
    发明申请
    MEMORY SYSTEM CAPABLE OF GENERATING NOTIFICATION SIGNALS 有权

    公开(公告)号：US20170315892A1

    公开(公告)日：2017-11-02

    申请号：US15140492

    申请日：2016-04-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen

    IPC: G06F11/27 ,  G06F13/16 ,  G06F11/22

    CPC classification number: G06F11/27 ,  G06F11/2289 ,  G06F13/1689

    Abstract: A memory system includes a memory device, a switch device, and a built-in self-test circuit. The memory device is for storing data and toggling a notification signal whenever a read operation or a write operation is completed. The switch device has a first input terminal for receiving an external clock signal, a second input terminal coupled to the memory device for receiving the notification signal, a select terminal for receiving a selection signal, and an output terminal for outputting a memory clock signal to the memory device. The memory clock signal is one of the external clock signal and the notification signal. The built-in self-test circuit is for outputting a control signal required by the memory device to perform the read operation or the write operation and check whether the memory device functions normally.

    Static random access memory
    3.
    发明授权
    Static random access memory 有权

    公开(公告)号：US10777260B1

    公开(公告)日：2020-09-15

    申请号：US16655220

    申请日：2019-10-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zih-Yu Chiu ,  Hsin-Wen Chen ,  Ya-Nan Mou ,  Yuan-Hui Chen ,  Chung-Cheng Tsai

    IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

    Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

    Content-Addressable Memory having Six-Transistor Content-Addressable Memory Cells
    4.
    发明申请
    Content-Addressable Memory having Six-Transistor Content-Addressable Memory Cells 审中-公开

    公开(公告)号：US20200234765A1

    公开(公告)日：2020-07-23

    申请号：US16254611

    申请日：2019-01-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zih-Yu Chiu ,  Hsin-Wen Chen ,  Yen-Yao Wang

    IPC: G11C15/04

    Abstract: A cell of a content-addressable memory (CAM) has a first switch, a second switch and a storage unit. A first end of the first switch and a first end of the second switch are coupled to a matchline. The first switch is controlled by a first search signal, and the second switch is controlled by a second search signal. The second search signal is complementary to the first search signal. The storage unit has a first inverter and a second inverter. The first inverter has a first latch node coupled to a second end of the first switch. The second inverter is cross-coupled to the first inverter and has a second latch node coupled to a second end of the second switch.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20180374856A1

    公开(公告)日：2018-12-27

    申请号：US15632378

    申请日：2017-06-25

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hsien-Hung Tsai

    IPC: H01L27/108 ,  H01L27/11 ,  H01L29/24

    Abstract: The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.

    MEMORY DEVICE AND METHOD FOR DRIVING MEMORY ARRAY THEREOF
    8.
    发明申请
    MEMORY DEVICE AND METHOD FOR DRIVING MEMORY ARRAY THEREOF 有权
    用于驱动其阵列的存储器件和方法

    公开(公告)号：US20140160861A1

    公开(公告)日：2014-06-12

    申请号：US13707611

    申请日：2012-12-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen

    IPC: G11C7/10 ,  G11C7/00 ,  G11C7/12

    CPC classification number: G11C7/12 ,  G11C11/419

    Abstract: A memory array includes a plurality of columns of memory cells and each column of memory cells of the memory array is coupled to a local voltage source, a bit line, and a bit line bar. Provide a working voltage to pre-charge the bit line and the bit line bar of the column of memory cells when a memory cell of the column of memory cells is selected to be read, and meanwhile use local voltage sources coupled to remaining columns of memory cells of the memory array to provide high voltages lower than the working voltage to pre-charge bit lines and bit line bars of the remaining columns of memory cells.

    Abstract translation: 存储器阵列包括多列存储器单元，并且存储器阵列的每列存储器单元耦合到本地电压源，位线和位线条。 当选择存储单元列的存储单元被读取时，提供工作电压以对存储器单元列的位线和位线条进行预充电，同时使用耦合到剩余存储列的本地电压源 存储器阵列的单元以提供低于工作电压的高电压以对存储器单元的剩余列的位线和位线条进行预充电。

    Content-addressable memory having six-transistor content-addressable memory cells
    9.
    发明授权
    Content-addressable memory having six-transistor content-addressable memory cells 有权

    公开(公告)号：US10885981B2

    公开(公告)日：2021-01-05

    申请号：US16254611

    申请日：2019-01-23

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Zih-Yu Chiu ,  Hsin-Wen Chen ,  Yen-Yao Wang

    IPC: G11C15/04

    Abstract: A cell of a content-addressable memory (CAM) has a first switch, a second switch and a storage unit. A first end of the first switch and a first end of the second switch are coupled to a matchline. The first switch is controlled by a first search signal, and the second switch is controlled by a second search signal. The second search signal is complementary to the first search signal. The storage unit has a first inverter and a second inverter. The first inverter has a first latch node coupled to a second end of the first switch. The second inverter is cross-coupled to the first inverter and has a second latch node coupled to a second end of the second switch.

    Array of dynamic random access memory cells
    10.
    发明授权
    Array of dynamic random access memory cells 有权

    公开(公告)号：US10032777B1

    公开(公告)日：2018-07-24

    申请号：US15613288

    申请日：2017-06-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hung-Chan Lin ,  Ting-Hao Chang ,  Hsien-Hung Tsai

    IPC: H01L27/108 ,  G06F12/0846

    Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

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