公开(公告)号：US10580499B2

公开(公告)日：2020-03-03

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  H01L27/112 ,  H01L27/02 ,  G11C17/12 ,  G06F17/50 ,  G11C7/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

公开(公告)号：US10352986B2

公开(公告)日：2019-07-16

申请号：US15164129

申请日：2016-05-25

Applicant: United Microelectronics Corp.

Inventor： Hsin-Pang Lu ,  Hsin-Wen Chen

IPC: G05F1/56 ,  G01R31/26 ,  H01L49/02 ,  H01L27/092 ,  H01L21/8238

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

公开(公告)号：US20170345720A1

公开(公告)日：2017-11-30

申请号：US15164129

申请日：2016-05-25

Applicant: United Microelectronics Corp.

Inventor： Hsin-Pang Lu ,  Hsin-Wen Chen

IPC: H01L21/8234 ,  H01L21/66 ,  G05F1/56 ,  H01L49/02 ,  G01R31/26

CPC classification number: G01R31/26 ,  G05F1/56 ,  H01L21/823892 ,  H01L27/092 ,  H01L28/40

Abstract: A method for controlling voltage of a doped well in a substrate is provided. The substrate and the doped well are in different conductive type. The method includes applying a substrate voltage to the substrate while a well power for applying a well voltage to the doped well is turned off. The method also includes detecting a voltage level of one of the doped well and the substrate to judge whether or not a voltage target is reached. The well power is turned on to apply the well voltage to the doped well when the voltage level as detected reaches to the voltage target.

公开(公告)号：US09093131B2

公开(公告)日：2015-07-28

申请号：US14108360

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsi-Wen Chen ,  Hsin-Pang Lu

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/22 ,  G11C16/28 ,  G11C2207/2227

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

公开(公告)号：US20150170718A1

公开(公告)日：2015-06-18

申请号：US14108360

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsi-Wen Chen ,  Hsin-Pang Lu

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/22 ,  G11C16/28 ,  G11C2207/2227

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

Abstract translation: 读出放大器电路可用于非易失性存储器的读取操作。 读出放大器电路包括第一预充电电路，第二预充电电路，偏置电路，使能电路，电流镜，第一比较器，第二比较器，缓冲器和计数器。 当前镜像能够放大存储器单元的单元电流，以防止错误，并且随着存储器单元的擦除计数增加而缩短或维持访问时间。

公开(公告)号：US11294577B2

公开(公告)日：2022-04-05

申请号：US16831716

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Hua Lu ,  Hsin-Pang Lu

IPC: G06F3/06 ,  G06F11/08 ,  G06F16/22

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.

公开(公告)号：US20210263656A1

公开(公告)日：2021-08-26

申请号：US16831716

申请日：2020-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiao-Hua Lu ,  Hsin-Pang Lu

IPC: G06F3/06 ,  G06F11/08 ,  G06F16/22

Abstract: A non-volatile memory includes a plurality of data storage units arranged in an array, a plurality of redundant data storage units arranged in at least one row and a plurality of redundant address storage units arranged in at least one row. A storage size of each of the data storage units is word. Each of the data storage units is addressable by a row address and a column address. One of the redundant data storage units in a first column is configured to substitute for one of the data storage units in a second column. One of the redundant address storage units in a third column is configured to record the row address representative of the substituted one of the data storage units.

公开(公告)号：US20150095728A1

公开(公告)日：2015-04-02

申请号：US14040752

申请日：2013-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Hsi-Wen Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai ,  Hsiao-Chieh Sung ,  Yin-Ju Hsiao

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G11C29/006

Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.

Abstract translation: 用于非易失性存储器的测试方法包括将第一组数据写入非易失性存储器中的一组地址，从该地址集中读取第二组数据，以及将第一组数据写入到 如果第一组数据和第二组数据不相同，并且将第一组数据写入地址集合的次数小于预定数量，则再次寻址。

公开(公告)号：US08724404B2

公开(公告)日：2014-05-13

申请号：US13652422

申请日：2012-10-15

Applicant: United Microelectronics Corp.

Inventor： Shi-Wen Chen ,  Hsin-Pang Lu ,  Chung-Cheng Tsai ,  Ya-Nan Mou

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4074 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/4074 ,  G11C16/30 ,  G11C29/021

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract translation: 电源电压产生电路包括比较单元，电压电平控制单元和电压调节器电路。 比较单元被配置为将存储器阵列的输入数据和输出数据彼此进行比较，从而生成比较结果，其中输出数据是存储在由程序操作处理的存储器阵列的多个存储器单元中的存储数据， 并且比较结果表示存在于输出数据和输入数据之间的不同位的数量。 电压电平控制单元被配置为根据比较结果产生控制信号。 电压调节器电路被配置为为存储器阵列提供电源电压，并根据控制信号调节电源电压的值。 还提供了用于存储器阵列的供应生成电路的存储器和操作方法。

公开(公告)号：US20190043587A1

公开(公告)日：2019-02-07

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  G06F17/50 ,  H01L27/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.