公开(公告)号：US20210183944A1

公开(公告)日：2021-06-17

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US10978122B1

公开(公告)日：2021-04-13

申请号：US16796953

申请日：2020-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Ya-Lan Chiou ,  Chun-Hsien Huang ,  Chih-Wei Tsai ,  Hsin-Chih Yu ,  Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Jhen-Siang Wu ,  Po-Chun Yang ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22

Abstract: A memory includes (n−1) non-volatile cells, (n−1) bit lines and a current driving circuit. Each of the (n−1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n−1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n−1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n−1) non-volatile cells.

公开(公告)号：US11018185B1

公开(公告)日：2021-05-25

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US10651235B1

公开(公告)日：2020-05-12

申请号：US16296225

申请日：2019-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jhen-Siang Wu ,  Po-Chun Yang ,  Yung-Ching Hsieh ,  Zong-Sheng Zheng ,  Jian-Jhong Chen ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.