公开(公告)号：US09978795B1

公开(公告)日：2018-05-22

申请号：US15401087

申请日：2017-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jy-Hwang Lin ,  Wen-Chieh Wang ,  Tien-Shang Kuo ,  Fu-Hsuan Chu ,  Hua-Wei Peng

IPC: H01L31/00 ,  H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14625 ,  H01L23/562 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14643 ,  H01L27/14678

Abstract: A semiconductor structure includes a substrate, a plurality of image sensing devices formed in the substrate, at least a passivation layer formed on the substrate, a plurality of first metal patterns formed on the passivation layer, a plurality of gaps formed between the first metal patterns, an insulating layer lining the gaps, and a plurality of light-guiding structures respectively formed in the gaps. The light-guiding structures respectively include an anchor portion and a body portion, and bottom surfaces of the anchor portions being lower than top surfaces of the first metal patterns.

公开(公告)号：US09741826B1

公开(公告)日：2017-08-22

申请号：US15299268

申请日：2016-10-20

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on the substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US09954099B1

公开(公告)日：2018-04-24

申请号：US15631820

申请日：2017-06-23

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US09941220B2

公开(公告)日：2018-04-10

申请号：US15008432

申请日：2016-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Tai Hsu ,  Tien-Shang Kuo ,  Yen-Chuan Chen ,  Chih-Hao Cheng

IPC: H01L23/00 ,  H01L23/544 ,  H01L23/58 ,  H01L21/784 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/82

Abstract: An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.

公开(公告)号：US20180114858A1

公开(公告)日：2018-04-26

申请号：US15631820

申请日：2017-06-23

Applicant: United Microelectronics Corp.

Inventor： Cheng-Hsun Chung ,  Shih-Teng Huang ,  Tien-Shang Kuo

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/36 ,  H01L23/535 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/7816 ,  H01L21/285 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/36 ,  H01L29/402 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/66613 ,  H01L29/66681 ,  H01L29/7824

Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.

公开(公告)号：US20170179044A1

公开(公告)日：2017-06-22

申请号：US15008432

申请日：2016-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Tai Hsu ,  Tien-Shang Kuo ,  Yen-Chuan Chen ,  Chih-Hao Cheng

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/544 ,  H01L23/585 ,  H01L24/16 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/24051 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/82047 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/82

Abstract: An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region.